The Investigation Of Parasitic Capacitance And Process Variations In Complementary Field-effect Transistor(CFET)

With Moore’s Law,Fin FETs and NSFETs have become the mainstream core device in the IC industry at 5nm and 3nm nodes.However,further miniaturization of device size will pose serious challenges to patterning and maintaining gate control.Meanwhile,as the device size gradually approaches the physical limit,quantum confinement effects become significant.Complementary field-effect transistor(CFET)is proposed to continue Moore’s Law by folding two complementary FETs.CFET consists of vertically stacked n-FET and p-FET,with the top and bottom devices sharing a common gate to control the switching of FETs.Due to the huge area benefits from 3-D vertical stacking and the inheritance of traditional devices for channel structures,CFETs offer significant combined power-performance-area-cost advantages,making them one of the highly concerned candidates for the 3nm and beyond nodes.However,due to the increased longitudinal dimension and the existence of the 3-D gate-all-around structure,the parasitic capacitance of CFET is becoming more significant,which has become the main bottleneck of the high-performance IC design.The modeling of the parasitic gate fringe capacitance is useful to evaluate the effect of device dimension scaling on the parasitic capacitance,thus providing a theoretical basis for reducing the parasitic capacitance and improving the frequency characteristic,and achieving accurate simulation and design of CFET-based IC.Another problem associated with the scaling of device dimension is that the effect of process variations becomes more severe,resulting in large fluctuations in circuit power and performance.Evaluation and modeling studies of key process fluctuation sources in nanoscale CFET devices are the cornerstone of predicting the variability of CFET electrical characteristics and establishing a process volatility-aware CFET circuit design architecture.To address the above issues,this paper conducts an in-depth study on structural optimization,gate fringe parasitic capacitance,and process variation modeling of the nanoscale CFET device.The main research contents and results are as follows.First,based on TCAD simulation,the DC/AC characteristics of Fin-based,nanowire(NW)-based and nanosheet(NS)-based CFETs are investigated,focusing on the structural size dependence.Firstly,constructing 3nm node Fin-CFET device,according to the CFET process flow and process compatibility,extending the device structure to NW-CFET and NS-CFET,and verification of the simulation platform was achieved by calibrating with the experimental data.Fin-CFET,NW-CFET and NSCFET designs are investigated from the perspective of DC/AC characteristics by using TCAD simulation tool.The results show that NS-CFET maintains both better gate control and current driving capability than Fin-CFET and NW-CFET under the trend of device miniaturization.Unlike conventional Fin FET/NSFET,due to the presence of N/P separator layer,which acts as an insulator between source/drain electrodes of the top and bottom devices,the longitudinal dimension of the gate is stretched.Reducing the N/P separator thickness can reduce the parasitic capacitance and intrinsic delay;however,if the thickness of the N/P separator is too small,it will lead to severe electric field coupling between the source/drain and the cross-layer channel,and then lead to CFET performance degradation or even failure.Second,the existence form and introduction mechanism of the gate fringe parasitic capacitance in CFET devices are explored,and an accurate physical model of the CFET gate fringe parasitic capacitance is realized by creating the testkey structure independently.Firstly,based on the spatial distribution of parasitic capacitance in 3-D Fin-CFET,NW-CFET and NS-CFET,the gate fringe capacitance is divided into simple basic parallel-plate capacitance,perpendicular-plate capacitance or coplanar-plate capacitance structure,and then an accurate analytical physical model of the CFET gate fringe parasitic capacitance is established by the conformal mapping method,focusing on the dependence of the parasitic capacitance on the key device physical parameters.Compared with the results of 3-D field solver,Raphael,the proposed parasitic capacitance model has high accuracy with a maximum root-mean-square error of 3.11%.Finally,the accuracy of the proposed parasitic capacitance model in circuit simulation is verified by the study of the transient response of the CFET inverter.Based on the proposed model,it is evaluated that gate fringe parasitic capacitance leads to a maximum of 57% increase in the delay and a maximum of 66% in the energy consumption of CFET-based standard cell circuits.Third,the impact of nanoscale random process fluctuations on CFET device performance is accurately evaluated.Taking 3nm NS-CFET as an example,for the key process fluctuation sources,including metal work function variation(WFV),line edge roughness(LER),gate edge roughness(GER)and random doping fluctuation(RDF),simulation investigation of the morphology-related roughness fluctuations(LER and GER)through MATLAB-TCAD method and atomic-level random variation sources(WFV and RDF)are implemented.The results show that the effect of GER is more significant in p-FETs compared to conventional NSFET,mainly due to the combined effect of the shared common metal gate and the p-WF liner,and that thickening the pWF liner can improve this effect.The other fluctuation sources are not significantly different from conventional devices.The effect of RDF is negligible in the case of lightly doped channels.The evaluation of the overall process fluctuations in CFET shows that,for the p-FET,GER causes a dramatic fluctuation in the subthreshold swing and an increment of 8.6% in DIBL fluctuation,which greatly disrupts the gate control capability of the p-FET in CFET.Fourth,a compact physical model of CFET devices containing stochastic process fluctuations is established,and accurate simulation and evaluation design of CFETbased circuits with process fluctuation awareness is realized.Based on the simulation study of key process fluctuation sources in 3nm NS-CFET devices,WFV,LER and GER are modeled to establish a BSIM-CMG compact model of CFET with process fluctuation by combining the physical mechanisms and statistical regularity of random fluctuation sources and validated with TCAD simulation results,with an accuracy of0.98X(n-FET)/1.12X(p-FET)for threshold voltage and 0.88X(n-FET)/0.91X(p-FET)for ON-state current.The effect of p-WF liner is considered in the GER model,and the dependence of GER effect on p-WF liner thickness is described by the exponential function factor.Then SPICE MC simulations of CFET-based SDC and RO circuits are performed using the proposed compact model to predict the effect of process variations on circuit performance.GER causes asymmetry in n-FET and p-FET fluctuations,resulting in CFET-based inverter energy consumption fluctuations of-14% to +17%.WFV has the largest effect on CFET-based RO Power-Performance-Area(PPA),with power consumption fluctuating from-10% to +12% compared to the nominal circuit without any process fluctuations.In this paper,the DC/AC characteristics,parasitic capacitance,structural dimension dependence and process fluctuation characteristics of 3nm CFETs are thoroughly investigated,and the response of device electrical characteristics to size miniaturization and process fluctuations,as well as a set of accurate parasitic capacitance models and CFET BSIM-CMG compact models with process fluctuation awareness,are proposed,which have important application value and guiding significance for the design optimization,process monitoring and control of CFET devices and circuits at 3 nm node and beyond.