Study On Semi-Analytical Model Of Parasitic Resistance In Source/Drain Region Of Fully-Depleted SOI MOSFET

MOSFET is the most widely used semi-conductor device currently,which is also the basic module of digital circuits,analog circuits and memory circuits.The continuously decrease of feature size brings much convenience to the development of integrated circuits,for example,it improves the integration degree of circuits,so the area and manufacturing cost of circuits are both decreased;the circuits own faster working speed and achieve richer functions.However,the decrease of feature size brings negative effect which reduces the performance of MOS devices.In order to solve these problems,for one thing,researchers use modern process,gate engineering and ditch engineering,to improve the performance of small-scale MOS devices;for another,they design some new structure devices to replace traditional bulk silicon MOS devices,such as SOI MOS devices,SON devices,double-gate MOS devices,gate-all-around MOS devices,strained-channel MOS devices and so on.At the same time when the channel of the device is reduced,the source/drain parasitic resistance has larger and larger effect to drive current of device,so the study on source/drain parasitic resistance of short-channel devices becomes more and more important.In this thesis,we study the source/drain parasitic resistance of fully depleted SOI MOSFET devices,establish the physical model of the device,give the solution problem,and get the analytical formula of potential and resistance of the source/drain area.Finally,we compare the calculated results with the simulation results.The specific content of the article is arranged as follows.First of all,we briefly introduced the bulk silicon MOSFET and SOI MOSFET.In view of the shortcomings of bulk silicon MOSFET,we introduced the fully depleted SOI MOSFET and the significance and research status of studying the source/drain parasitic resistance of MOSFET devices.Then,several classical methods to calculate the source/drain parasitic resistance are given.In this thesis,the extraction and modeling methods are mainly introduced,and examples of the two methods in practical applications are cited.The following is the physical modeling of the fully depleted SOI MOSFET source/drain region and the method of solving the source/drain resistance of the fully depleted SOI devices through the plane MOSFET.In this thesis,the source/drain parasitic resistance is divided into three parts.The lumped resistance in zone 1 can be obtained directly according to Ohm's law.When solving the distribution resistance in zone ? and ?,we need to find out the corresponding potential distribution first,and then get the relative resistance according to Ohm's law.Finally,the physical model is verified and analyzed.The potential difference in zone ? and ? is verified by the classical central difference method.The distribution of potential equipotential lines in the two cases of the same conductivity and different electrical conductivity is discussed respectively.The accuracy of difference method and modeling method is basically the same.After obtaining the potential,we can get the resistance of zone ?,? and ?,and compare the resistance of three regions with the data obtained by SILVACO simulation,and the maximum error is about 9.2%.At the end of this thesis,the effect of silicide deposition on the parasitic resistance under the electrode is also discussed,and it is found that the deposited silicide can effectively reduce the source/drain resistance.This thesis is based on the semi analytical method to solve the source/drain parasitic resistance.It has the advantages of high accuracy of numerical method,which also has the advantage of analytical method.There is a certain significance for the research of source/drain parasitic resistance.