Research On Extraction For Parasitic Resistance And Inductance Of VlSI Interconnects

Moore law has driven the scaling of digital electronic devices dimensions and performances over the last40years. As a result, logic components in a microprocessor have shown dramatic performance improvement. On the other hand, an on-chip interconnect which was considered only as a parasitic load before1990s became the real performance bottleneck due to its extremely reduced cross section dimension. Now, on-chip global interconnect with conventional Cu/low-k and delay optimized repeater scheme faces great challenges in the nanometer regime, imposing problems of slower delay, coupling,higher power dissipation and limited bandwidth. On the otherside, how to get huge quarter of parasics parameter for the on-chip interconnects and do high capacity simulation is still the main task we are facing in the current verification.The method of moments (MOM) is a practice method for parasitic resistance and inductance parameter extraction of the interconnect. However, due to the rectangular discreditations used in the traditional MOM, there are some difficulties happened when using MOM to do extraction for a real whole chip interconnects, especially when technologic nodes bellows90nm. For example, the interconnect cross section may mot be a rectangular any more, the interconnect surface is rough surface. Based on the theory and result of MOM, the main topic includes:(1) improving the meshing generation the method of moments, introduced hybrid mesh (triangle+rectangle) to calculate the resistance and inductance parameter of any arbitrarily shaped section,(2) We explore the method of higher-order basis functions of MOM. The method reduces the number of unknowns in the traditional moment method and improves parameter extraction efficiency. Some analytic formulas for matrix elements of the electric resistance inductance are given.(3) Based on the results of numerical method, optimization method such as Levenberg-Marquardt are used to get analytical formulas of resistance for different structure interconnect, which further improve parameters extraction efficiency of on-chip interconnect.(4) Being influenced by the skin effect, the internal inductance of wires gradually decreases with increased frequency and internal inductance show the inductance frequency characteristic. In order to study the broadband effect of interconnect, internal inductance need to be studied. The least squares method and the Lagrangian method can be used to get the analytic form of internal inductance.(5) We study the whole inductance including internal inductance and external inductance and the analytic form of three-dimensional self-inductance of DC is educed by Taylor series expansion method.The improved MOM can be applied to analyze interconnect parasitic parameters of any arbitrarily shaped section and the result can approach the reality; the method of higher-order basis functions of MOM improves computational efficiency and it can save90%computational time at least compared traditional MOM; The proposed resistance analytic formulas can be used in three simple interconnect structures, greatly reducing the computation time; The internal inductance analytical formula is applied to the circuit model used to simulate the skin effect, which provides convenience in the time domain analysis of parasitic parameters. Meanwhile, the DC self-inductance analytical formula is proposed to avoid singular points in a numerical method.