Study And Design Of 16-bit Low-power Audio Discrete-time Sigma-delta Modulation

In the family of high-end general-purpose analog chips,high-performance ADCs have always been a difficult point and hot spot for research due to their strict requirements for circuit matching,distortion,and noise.In order to obtain high-quality sound effects,16-bit or higherresolution audio ADCs are more and more widely used in Bluetooth and Hi-Fi players.SigmaDelta ADC has attracted more and more attention due to its advantages such as high resolution,high integration,and low requirements for component matching.However,due to the use of oversampling technology in the Sigma-Delta modulator(SDM),the core module of the SigmaDelta ADC,a higher sampling frequency will result in higher power consumption.Therefore,designing and realizing SDM with high performance and low power consumption has become a current research hotspot.This thesis aims at the limited signal-to-noise ratio that can be achieved by traditional single-bit modulators and the instability of high-order systems.A second-order integrator,fourbit quantizer and 128 times oversampling rate are used to achieve a high signal-to-noise ratio.And to achieve better SDM stability.In view of the high power consumption of the traditional structure SDM,this thesis adopts the feedforward structure,uses two sets of the same sampling capacitor to sample the feedback DAC and the input signal to reduce the output swing of the op amp,and uses the SC-CMFB without static power consumption as strategies such as the common-mode feedback circuit of the op amp reduce the power consumption of the SDM system.Aiming at the nonlinear problem of modulators using multi-bit quantizers,this thesis uses a comparator with an offset cancellation structure to reduce the gain error of the quantizer,and uses a DWA circuit to reduce the nonlinearity of the feedback DAC.This thesis designs and optimizes the transfer function of the SDM system in the delsig toolbox in MATLAB,analyzes the stability of the system,and conducts system-level simulation to verify the performance of the system.Using the non-ideal model of the SIMSIDES toolbox in MATLAB,the system's performance requirements for integrators,quantizers,feedback DACs,etc.are obtained by simulation.Based on the UMC0.18?m CMOS process,an op amp with low power consumption,high gain bandwidth product,large slew rate,fully differential Flash ADC with good linearity,and high-speed comparator with low offset error are designed.And using these module circuits,an SDM with higher performance and lower power consumption is designed.The simulation results of this design show that the total power consumption of the chip is about 1.194 m W;when the test signal is a 20 KHz sinusoidal signal and the sampling clock signal is 5.12 MHz,the signal-to-noise ratio is 101.3dB,which is about 16.5bits.