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Study And Design Of Low Power Consumption And High Precision Cascaded Delta-Sigma Modulator

Posted on:2018-05-28Degree:MasterType:Thesis
Country:ChinaCandidate:C LiuFull Text:PDF
GTID:2428330518458662Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the development of digital signal processing and integrated circuits,analog to digital converter(ADC)increasingly requires high precision in the field of communications and other audio field.Since Delta-Sigma ADC could increase the resolution of the converters by adopting oversampling technology and noise shaping,it has been widely used.Delta-Sigma ADC has plays a more and more important role in electronic equipment for high precision.Delta-Sigma modulator is the core module of Delta-Sigma ADC,but there is a problem of excessive power consumption.However,this problem exists in the design of Delta-Sigma modulator.So in this paper,we will design a low-power,high-performance Delta-Sigma modulator after making a deep study on it.This paper first introduces two key technologies to improve the performance of the modulator:the Zero Optimization and Noise Coupling,and they were used in single ring structure.Analysis shows,in the case of improve the accuracy of the modulator without use active devices,while reducing the power consumption in single ring structure.Secondly,in order to achieve the design goal of 22-bit high precise,We determine to use third-order two stages cascaded structure in this paper.Based on the technologies of Zero Optimization and Noise Coupling,we design three types of cascaded Delta-Sigma modulator.They are MASH 2-1,SMASH-MASH 2-1 and SMASH 2-1,respectively.The simulation test shows:when OSR is 256 and signal bandwidth is 1KHZ,the precise about MASH 2-1 and SMASH-MASH 2-1 is 26.80 bits and 22.59 bits,respectively;When OSR is 32 and the signal bandwidth is 1MHz,the precise of the third modulator is 22.90-bit precision.Finally,we analyze the non-ideal factors existing in the actual modulator,including the limited DC gain of the op amp,the unit gain bandwidth,the slew rate and the saturation voltage.And we model the clock jitter and thermal noise in switched capacitor of integrator.We conduct simulation experiment under the non-ideal conditions.And the simulation test shows:MASH 2-1 can still have 24.86-bit precision and its SNR is 151.4dB.
Keywords/Search Tags:Analog-to-Digital Converter, Delta-Sigma modulator, Zero optimization, Noise coupling, Cascade structure
PDF Full Text Request
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