Design And Performance Optimization Of Sigma-Delta Modulator Based On Multi-bit Quantization

The constantly improving integrated circuit design and manufacturing technology provide hardware conditions for the implementation of complex data processing algorithms.However,the mainstream data processing algorithms can't directly deal with the analog signal obtained by sensors.Under the circumstance,analog to digital converter(ADC)which can convert the analog signal into a digital signal is needed.With the popularization of the Internet of Things technology,the demand for ADC has increased year by year,which makes high-precision ADCs have gradually become a research hotspot at home and abroad.In order to meet the requirements of digital silicon micromachined gyro sensor for 20 kHz signal frequency and high-precision analog-digital conversion,a circuit of multi-bit quantization Sigma-Delta modulator in Sigma-Delta ADC was designed in this paper.The TOP-DOWN design methodology was used in circuit design.The system level design of the circuit was first performed.According to the requirements of the modulator performance for the system,an appropriate modulator structure was selected,and the noise transfer function was designed by SD-toolbox to iterative optimal modulator.Then,select the appropriate module to meet the system-level design requirements,analyze the influence of the non-ideal characteristics of each module of the modulator on the noise shaping function of the modulator and the effect of the incidental noise on the noise characteristics of the modulator,and use Simlink to set up the behavior for each non-ideal characteristic thus to accelerate the determination of parameters of each module.Finally,according to the influence of parameter indexes and non-ideal characteristics of the module-level circuit,the optimized circuit was selected to realize the circuit-level design and draw layout of the entire modulator.In this paper,some performance of modulator such as dynamic range and signal overload was optimized.A 33-level quantizer was used to improve the dynamic range of the modulator and input overload;The use of multiple feedforward structures reduces the system's performance requirements for the adder and reduces the circuit power consumption;Through the digital circuit design DWA(Data Weighted Averaging)dynamic matching algorithm to suppress harmonic distortion of the multi-bit quantized modulator caused by the feedback DAC mismatch pair.The final designed modulator is a single-ring 4th-order,33-level quantizer,multi-channel feed-forward structure,and DWA digital dynamic matching architecture design.The clock frequency is 3.2MHz,the oversampling ratio is 64,and the signal bandwidth is 25 k Hz.Based on this,the performance simulation and analysis of the modulator circuit schematic were carried out.The modulator has a dynamic range of 138 dB(A Weighted)in the 25 kHz signal bandwidth,and the input signal overload is-0.3dB.The third harmonic distortion is-126.8dB when input sine signal at 3.125 kHz and-6dB amplitude.The layout of the modulator was finally drawn using a 0.35 ?m CMOS process,and the chip area was 4.7 mm2.After the layout simulation of the modulator,the result shows that the modulator has a dynamic range of 132 dB(A Weighted)in the 25 kHz signal bandwidth,and input signal overload of-0.5 dB.The third harmonic distortion is-121 dB when input sine signal at 3.125kHz and-6dB amplitude.