Research On Key Technologies Of Low Power Delta-Sigma Modulator

As the bridge between analog signal and digital signal,the performance of analog-to-digital converter directly determines the quality of the processed signal.With the emer-gence of portable electronic equipment,the development of the Internet of things,the ap-plication of precision measuring instruments,biological signal acquisition,high-quality audio equipment,sensor interface and other fields,high precision and low power con-sumption have become the main development direction of analog-to-digital converter.However,the speed,accuracy and power consumption of Delta-Sigma ADC are mutu-ally restrictive,and it is of no reference significance to simply discuss one of these indi-cators.The Schreier figure of merit(Fo M_s)is usually used to measure its overall perfor-mance,that is,while ensuring the accuracy and speed of the modulator,the power con-sumption is minimized and the figure of merit is improved.Aiming at the research of Delta-Sigma Modulator in the analog part of delta sigma ADC,this thesis studies its low-power technology from the system level and circuit level.Based on the Cadence platform,a high-precision,low-power Delta-Sigma is designed us-ing 0.18?m CMOS process,in order to achieve high Schreier merit,i.e.energy efficiency.Firstly,according to system analysis and design indicators,a low-power,full-feed-forward3-order 4-bit quantizer architecture is selected,and behavioral simulation modeling is per-formed based on MATLAB/SIMULINK.Considering the non ideal factors of the system,DWA(Data Weighted Averaging)technology is used to improve the nonlinear problems caused by multi bit feedback DAC,and the main design parameters of the system and circuit modules are obtained.Then,the low-power technology is analyzed and selected at the circuit level.According to the special timing of the system,a 4-bit SAR(Successive-Approximation Registor)quantizer with feedforward summation is proposed.The passive summation does not consume static power consumption,and the whole circuit module and modulator are simulated and verified.Finally,the layout design and verification of each sub module in the modulator are carried out,and the overall layout design of the system is given.The signal bandwidth is 8k,the sampling frequency is 1.024M,the supply voltage is 3.3V,and the pre-simulation results show that the design achieves a signal-to-noise dis-tortion ratio of 106.95d B,the dynamic range is 120d B,the power consumption is 2.3m W,and the Optimal Schreier value is 172.36d B,which meets the design specifications.