Study And Application Of SRAM In Quantum-dot Cellular Automata

Quantum-dot cellular automata(QCA)is a new nanodevice that is expected to replace the traditional CMOS circuit.In theory,QCA has the advantages of ultra-low power consumption,ultra-high integration and ultra-high conversion speed.In recent decades,CMOS technology has become increasingly perfect and mature,and the characteristic size of devices has reached the order of magnitude of several nanometers.The resulting problems such as quantum effects and leakage current,as well as manufacturing processes,need to be solved.The emergence of QCA,with its unique advantages is expected to replace CMOS in the future in the position of digital integrated circuits.Since QCA was put forward,many researchers have made excellent achievements in the design of complex systems of basic logic devices and basic computing units.This paper mainly discusses how to design memory units and optimize the design of memory with a certain scale in QCA circuit.Memory unit plays a very important role in VLSI.In the design of large scale memory,Static random access memory(SRAM)is the most important logical unit.In this thesis,a new SRAM memory unit with loop-based structure is proposed.The proposed storage unit is realized by a D-latch.Then,a three-layer structure of 4-bit SRAM and 16-bit SRAM are proposed.The proposed 1-bit SRAM circuit can reduce the Cost function by 35% and the power consumption by 36% compared with the best memory cell structure published.In terms of circuit area,cell number and circuit delay,the 4-bit SRAM is greatly improved compared with the circuits with the same result.The complexity of the 4-bit SRAM is reduced by 67% and the complexity is also reduced by34.8% compared with the existing structure with the lowest cost function.The proposed16-bit SRAM demonstrates that the designed memory is scalable on large and complex circuits.In addition,the Cost function of the proposed 16-bit SRAM is reduced by 77.8%compared with the existing circuit with the simplest structure,and the power consumption of the proposed 16-bit SRAM is reduced by 41.9% compared with the CMOS circuit based on the 15 nm Nan Gate library with the same structure.This paper also focuses on the application of multibit SRAM circuits.The QCA 4-input look up table circuit and the configurable logic block circuit based on Xilinx XC4000 are designed with the proposed16-bit SRAM.The basic structure of the 4-input look-up table consists of a 4-16 decoder,a 16-bit SRAM,and a 16-to-1 multiplexer.These basic structures are optimized in terms of cell number,circuit area,and latency.Compared with the CMOS circuit based on 15 nm Nan Gate library with the same structure,the proposed QCA 4-input look-up table reduces the power consumption by 60.8%.Functional correctness of the proposed designs has been proved by using QCADesigner 2.0.3.and their energy dissipation is also computed by QCADesignerE.