Research On Design Technology Of High Speed Wide Frequency Range Phase-locked-loop

A phase-locked loop(PLL)is a circuit used to generate a signal with the same phase as the input signal.Since it was first invented,it has undergone many developments and innovations and has various types,which can generally be divided into linear PLL(LPLL),mixed-signal PLL(DPLL),and digital PLL(ADPLL).Each has different applications,such as a frequency synthesizer,digital data clock recovery,FM demodulation circuit,etc.The background of this subject is based on the research of the high-speed and high accuracy analog-to-digital converter(ADC)project.The purpose is to design the PLL module that provides the JESD204B interface clock signal in the ADC.With the improvement of converter accuracy and speed,the parallel data transmission interface has been replaced by high-speed serial data transmission interface gradually.One of the key modules of the high-speed serial data interface is the high-speed clock circuit,which has a direct impact on the completion of the correct data transmission.Therefore,it is of great significance to study the clock signal generation circuit of the interface.This subject requires a PLL with output frequency cover from 6GHz to 15GHz based on65nm CMOS process.So,the charge pump(CP)type PLL is adopted for this subject.Among the PLL,an LC-type voltage-controlled oscillator(VCO)is used for its high operating frequency and low noise.To achieve high speed,wide frequency range and low phase noise,frequency band selection method is employed by using a programmable capacitor array(C-tank)and a programmable tuning capacitor array.At the same time,a low-dropout linear regulator(LDO)is designed for VCO as power supply to further optimize phase noise of VCO.To ensure the PLL performance like stability,locking speed and so on,the RC parameters value design is a key point,so,a parameters configurable loop filter is designed which can be configured reasonably according to the operating frequency of the PLL.The design of the CP mainly focus on solving its non-ideal effects that lead to current mismatches and voltage ripples,which will worsen the phase noise of the PLL.And a current self-calibration has been designed to further ensure the current matches.The divider adopts the pulse-swallow structure which is a combination of analog and digital divider,so it can not only achieve high-speed frequency division,but also realize a large frequency division range.At last,the circuit is designed and simulated as well as its layout is designed through Cadence.The output frequency range of PLL can achieve 5.45GHz?16.41GHz coverage,and the clock jitter is 2.88ps and the power consumption is 37m W at 5.45GHz as the jitter is3.05ps and power consumption is 60m W at 16.41GHz.The phase noise of the VCO is-116d Bc/Hz@1MHz as its frequency is 5.45GHz and is-87d Bc/Hz@1MHz while its frequency is 16.41GHz.The layout area is 0.9022mm~2.All the results show that the designed PLL meets the design requirements of this project.