Research Of The Storage And Transpose Structure In Heterogeneous Multi-core SoC

The memory wall problem is one of the hottest problems in Multi-processor System on Chip (MPSoC) design. It becomes even worst in heterogeneous MPSoC because the enhanced computing performance of heterogeneous computing nodes will bring much more memory operations. In this thesis, this problem is studied in two ways. Firstly, a packet circuit connecting (PCC) based NoC is constructed. And DDR3SDRAMs are directly to PCC to enhance the throughput. The new architectures of matrix transpose is proposed to improve the transpose efficiency. The major work and results are as follows:Firstly, DDR3SDRAM is used as the main memory, and a DDR3wrapper is designed to connect SDRAM directly to PCC on chip network. With detailly analysis of the DDR3controller interface, the DDR3Wrapper is divided into a plurality of modules and modules are designed with top-down design method.Secondly, to improve the matrix transpose efficiency, traditional transpose method is improved by using row-write, row-read operation method. The transpose module has been designed by using DDR3in the real-time image system. Through the analysis of the transpose structure and the features of DDR3access, DDR3memory is divided into a plurality of memory blocks to store the image data. Experiments results show that the proposed method can improve the efficiency of matrix transpose three to four times.Finally, a Ping-Pong based DDR3memory controller is designed, and the traditional transpose method is improved by using the row-write column-read method. Experiment results show that the storage efficiency has an improvement of100%.