Research On Multi-mode Arithmetic And Logic Operation Circuit Based On SRAM

In the era of big data,when facing data-intensive applications,existing computing structures will increase energy consumption and latency due to large amounts of data handling and bandwidth limitations.In order to solve the energy consumption and delay caused by memory access and data handling,the academic community has proposed an arithmetic and logic operation circuit based on SRAM to implement arithmetic and logic operations in the memory.Existing SRAM-based arithmetic logic operation circuits have a relatively single compute mode,and the performance of the circuit will be limited when faced with scenarios where external inputs and operations are performed between storage units.This thesis proposes a multi-mode arithmetic logic operation circuit based on SRAM,which can not only perform normal data reading and writing like traditional SRAM,but also complete various Boolean logic operations in the memory,combining storage and compute.In addition to the single operation mode that can complete the operation between the storage units,the circuit in this thesis can also realize the operation between the external input and the storage unit,and further reduces the memory compared with other arithmetic logic operation circuits based on SRAM.The number of memory accesses,thereby reducing energy consumption.In addition,the circuit in this thesis also supports both bit-parallel and bit-serial compute methods.With the help of peripheral computing circuits,it can complete bit-serial and bit-parallel arithmetic and logic operations.In the case of limited storage arrays,bit-serial compute method enables the circuit to have greater throughput,while the bit parallel calculation method can increase the calculation speed.This thesis is based on SMIC 0.13 um CMOS process,under 1.2V working voltage,the circuit is simulated and performance analyzed,and performance comparison with other SRAM-based arithmetic logic operation circuit structures is carried out.In the mode of operation between storage units,the structure of this paper has less energy consumption in the realization of XOR logic,and through the bit parallel compute method,the circuit has a lower delay in the realization of multi-bit addition operations;In the serial compute method,when the circuit implements various arithmetic and logic operations in the storage array,it has a higher throughput than the bit parallel structure.In addition,when faced with multi-bit logic operations in external input scenarios,the circuit in this thesis has obvious advantages in energy consumption and delay through the realization of the immediate mode.In the end,this thesis carries out layout drawing and post-simulation analysis for the proposed circuit structure,and discusses the impact of physical realization on the circuit.