The Circuit Design Of In-memory Logic Operation And Multiplication Based On New 10T SRAM

In recent years,artificial intelligence technology has developed rapidly,and there are more and more highly data-centric applications related to artificial intelligence.However,since the storage and computation modules of the traditional von Neumann architecture are separated from each other,frequent information interactions between the two are required when processing data,which will incur huge costs in terms of latency and power consumption.Facing the massive data brought by artificial intelligence technology,the bottleneck of traditional computing architecture is increasingly prominent,making the development of dataintensive applications limited.The proposal of in-memory computing fundamentally breaks through the von Neumann bottleneck.Its core idea is to perform computing tasks in memory,integrate the integration of storage and computing,reduce data transmission between processors and memory,and improve the efficiency of data processing.Static RandomAccess Memory(SRAM)is widely used due to its performance advantages and has become one of the main research subjects in the field of in-memory computing.This article firstly introduces the research background and research progress of inmemory computing technology based on the limitations of the traditional computing architecture.Since this paper introduces the components of SRAM system architecture and the working principle of each part of the circuit,including memory array and peripheral auxiliary circuits,and then introduces several SRAM-based in-memory computing technologies in detail with the operation type as an entry point.In this paper,a series of research work has been carried out on SRAM in-memory computing technology.On this basis,a new 10 T cell circuit that can realize the return of operation results is proposed.The cell adds four transistors on the basis of the traditional 6T cell structure,which can realize basic read and write operations.The Boolean logic operation function and the back-storage of the operation result can be realized through a reasonable configuration cell port,and no additional memory is needed to store the operation result.In addition to the above functions,the new 10 T cell structure proposed in this paper can be used to realize the multi-bit multiplication function in the memory.The main strategy is to convert both the multiplied number and the multiplier into binary form,the multiplied numbers are stored in four adjacent memory cells in a row with certain regularity,and the multipliers are mapped to the input ports of the cells in the form of high and low levels,and finally,the final multi-bit multiplication result is obtained through digital circuit processing.A 128x128 10 T SRAM memory array is built using the smallest size transistors in a28 nm process,and the circuit was simulated and verified.The circuit are evaluated in terms of energy consumption,stability and speed dimensions.The results indicate that the power consumption and speed of the Boolean logic operation in the memory are 543 MHZ and16.39 f J/bit,respectively,at 0.6 the supply voltage.