Design And Implementation Of LDPC Coding Algorithm Based On IEEE 802.11ac

With the development of society,people's demand for wireless local area network technology is getting higher and higher.The improvement of wireless communication throughput and the reduction of delay are still the key research directions in the field of wireless communication.Channel coding can effectively improve the reliability and stability of data communication.How to improve channel throughput and reduce delay in channel coding mode is a hot research topic.Low-density parity check(LDPC)coding is one of the coding methods closest to Shannon's channel capacity.As a type of channel coding scheme that can approximate channel capacity,low-density parity check(LDPC)codes have low complexity coding.It has many advantages such as self-interlacing and low-error leveling,and thus has become an optional channel coding scheme for the recent wireless local area network standard(IEEE802.11ac).How to improve the throughput of LDPC coding and reduce the hardware resources occupied by codec modules has always been an important issue in LDPC codec.Based on the 802.11 ac wireless protocol,this paper designs an LDPC codec suitable for the new generation of WiFi wireless communication chips.The main research results and innovations are as follows:A new hardware architecture of the scrambler is designed.The original serial scrambling algorithm is transformed into a partial parallel scrambling algorithm,which solves the contradiction between the highest clock frequency and hardware area consumption of the system.According to the periodic cycle characteristics of the scrambling code sequence,the scrambling code sequence is stored in the ROM according to the minimum bit width length 26 bits of the input data bit width,and is read from the ROM when the input valid 250 kHz clock valid edge of each scrambler arrives.An integer multiple of the least significant bit width of the scrambling code sequence and a scrambling code exclusive OR operation.Such a partially parallel scrambling code implementation not only improves the throughput of the scrambler,but also seeks a balanced tradeoff between clock frequency and hardware area.An improved H matrix storage algorithm based on the three-element method is proposed,which significantly reduces the storage space of the H matrix.In this paper,for the characteristics of H matrix in 802.11 ac,the position of storing each non-zero element in the algorithm of storing the sparse matrix of the three-element method is improved to store only the number of cyclic shifts of each unit sub-matrix in the H matrix and its H matrix.The location in the area,which effectively reduces the storage space consumption in the codec.The hardware architecture of an LDPC encoder with sub-matrix parallel coding is designed to improve the throughput of the entire encoder.In this paper,the LU coding algorithm is used to realize the design of the encoder.At the same time,according to the characteristics of the 802.11 ac protocol,the H matrix is composed of a quasi-cyclic unit sub-matrix.The input of 312-bit bit-width data is transformed into 81-bit bit-width data for coding matrix operation.The H matrix data is read in parallel for encoding operation,and the bitwise XOR of the matrix operation is converted into a cyclic shift operation,which reduces the computational complexity and coding delay of the encoder.The MS minimum sum product decoding algorithm based on normalization correction is proposed.When the LDPC decoder has the same output error rate,the input signal signal-to-noise ratio is reduced by 10 db.In this paper,four improved decoding algorithms based on BP decoding algorithm are studied in depth.The simulation performances of different decoding and demodulation and decoding parameters in 802.11 ac are compared.Finally,the normalized modified MS is selected.The minimum sum product decoding algorithm implements the LDPC decoder in 802.11 ac.With the normalized modified minimum sum product decoding algorithm,the decoder performance is improved by about 10 db.A hierarchical parallel iterative LDPC decoder hardware structure is designed.The original H matrix is layered into 12 layers for parallel decoding iteration,which reduces the variable node storage space.In this paper,the variable nodes and check nodes are mutually iterated in a hierarchical and parallel manner.In this way,the storage space of the variable node is reduced to 1/12 of the original hardware structure,which significantly reduces the hardware resource consumption in the decoder.At the same time,the parallel decoding of the variable node and the check node makes the decoding delay of the decoder also reduced.