Current Steering Dac Design And Adaptive Cable Drive The Implementation

With the development of new semiconductor and digital communication technology, large numbers of advanced electronic products appear endlessly in industry of all kinds. For example, in the field of wireless communication, Mobile TV, which combines mobile phone with high density television (HDTV), is realized by installing the module of microwave digital television receiver on mobile phones. It can receive signal of digital television directly without the link of mobile communication network. This technology is the most innovative in the coming future.The people apperceive environment through analog signal, so all kinds of Electronic System converter result to analog signal to control electrical machines or as the input of video, audio equipment which satisfy the demand about seeing and hearing of people. Therefore, the Digital to Analog Converter (DAC) play the key function in Electronic System, which affect feasibility, reliability, stability of system and the people's impression about system's performance.The aim of this thesis is to design a high speed, high resolution current-steering DAC according to the characteristics of communication system. In the beginning, a brief introduction of basic concepts and categorization as well as merits and demerits of each kind of DAC is given. Meanwhile, the segmented current-steering architecture is selected for the designated DAC. After that, the random errors, system errors and dynamic performance are analyzed by matlab simulation. Segment ratio and area of LSB current cell are acquired from the results of matlab simulation. Finally, schematic and layout design are discussed and circuit simulation results are provided. In many applications, the analog signal which is the output of DAC is transferred by line, so a special circuit entitled Line Driver is needed. In this design, first we introduce the physical model of transmission line, and then we discuss the classic ClassAB buffer and its improvements, and at last the buffer and line driver function is realized without extra circuit and power dissipation. The output impedance matched the adaptive resistive load without loss of signal's voltage or current.This design uses Charter 0.35μm Mixed Signal 1P6M 1.8V process. The DAC SNDR can be realized 61.1dB@4.9MHz, and the line driver's SFDR can be under 51dB@5MHz with the adaptive resistor from 45Ωto 80Ω.