Design And Implementation Of Parallel Interface Memory Chip Test System

With the continuous development of the world integrated circuit industry,all kinds of integrated circuit equipment for memory requirements are getting higher and higher.Traditional memory is generally divided into non-volatile memory and volatile memory two kinds,non-volatile memory generally has high-speed but when power loss data can not be retained,On the contrary,volatile memory generally has low-speed but data power loss can be retained.Almost none traditional memory can combine the two advantages,but in recent years,with the research of memory technology has emerged a number of new memory chip.The better application prospect in these memory chips is mram(Magnetic Random Access Memory),which is currently in development due to infrastructure manufacturing process constraints.In order to ensure the stability of the chip's various functions A lot of testing work is required before a qualified memory chip is commercially available.so it is particularly important to find a flexible and inexpensive memory chip test system.Based on the study of the MRAM structure,this paper builds a functional test system for DDR4(Dual Date Rate 4)through the Microblaze processor.In this paper,the research content of the chip test system is divided into the following four parts:(1)The development background of the new memory and the current situation of international and domestic research,the structure and characteristics of the new nonvolatile memory,as well as the memory failure model and test algorithm.(2)Learn the digital part of the DDR4 protocol,Including pin functions,various interface commands,mode register configuration,DBI(Data Bus Inversion),DM(Data Mask),CRC(Cyclic Redundancy Check),Timing parameter requirements,etc.design the test system after in-depth study of the logic control method of DDR4 interface.(3)Carry out the selection of FPGA(Field-Programmable Gate Array)core board,and learn the power-on sequence and voltage requirements of the FPGA mainboard.Study the generation of clock signals and the interface communication mode between the host computer and the test system.The host computer supplies power to the core board through the Mini USB(Universal Serial Bus)interface,and through the USB-UART(Universal Asynchronous Receiver/Transmitter)circuit Send instructions to the test system.(4)The test system adopts the SOPC(System-on-a-Programmable-Chip)design method,and completes the interconnection between the test system and the memory chip through the embedded system hardware part built by IP cores such as Microblaze and GPIO(General-purpose input/output),and communicates with the host computer through a serial interface tool.Then,Generate DDR4 interface timing through API(Application Program Interface)function in the SDK(Software Development Kit).Finally,verify the test system on FPGA board.