Design And Implementation Of Functional Verification System Of High Speed DDR4 RCD Chip Based On FPGA

The rapid development of DDR has put forward higher and higher requirements for IC test system.The increasment of signal frequency and channel number bring many new probloms to multi-channel high-speed parallel signal processing,such as phase and timing processing,signal integrity,rate conversion.It is common to use ATE universal test platform for DDR test,which has high test design cost and system cost.It is necessary to develop specific test system for products with specific requirements,which can reduce test complexity and test costs while ensuring the completion of test requirements.There is little research on DDR4 registering clock driver(RCD),which is a key device to increase the capacity of memory system.Aiming at the requirement of high-speed and multi-channel parallel signal processing,this paper presents a test platform with convenient test,low cost and high reliability,taking DDR4 RCD chip as test object.The system uses FPGA as the main control chip,sends 37 channels high-speed excitation to the DDR4 RCD chip,receives 74 channels high-speed response,so as to judge the performance of RCD chip.The upper computer controls test process of RCD chip and outputs test results automatically.This paper proposes a scheme of source synchronization clock to solve the problem of delay variation in high-speed signal transmission,uses mixed-mode clock manager of FPGA to realize dynamically configurable clocks,and uses ISERDES and OSERDES function of FPGA to transmit and receive high-speed multi-channel parallel signals.Calibration mode of signals source synchronization technology is studied to solve the error code of high-speed parallel transmission.Aiming at the problem of signal integrity in high-speed signal transmission,this paper carries out modeling and simulation of key signals to guide PCB design.High-speed DDR4 RCD chip verification system based on Kintex-7 series of FPGA is implemented in this paper.The signal speed of single channel is up to 1600 Mbps,the transmission bandwidth is up to 59 Gbps,and the receiving bandwidth is up to 118 Gbps.This design can meet the test requirements and provide a new low cost test plan for DDR4 RCD chip.