Fpga-based Pci Master Interface Design

PCI(Peripheral Component Interconnect) Local Bus is one of the high performance computer system local bus being used broadly today. It's interface has become the very important circuit module of most computer systems. The virtues of flexible programmability, function optimization according to PCI card, compact system design and substantial cost saving can be achieved by utilizing programmable devices when implementing PCI interfaces.On account of actual demand, an IP core of 32bits/33MHz PCI interface module based on FPGA has been designed by virtue of VHDL, and the 32 bits Microblaze processor soft core has been embedded into this FPGA. So, a fast and highly efficient PCI Master/Slave interface, a local processor and other control logic are integrated on one chip of FPGA.The contents in this thesis are as follows.1. The architecture concept, the top-to-down function blocks description, the local side communication protocol and other consideration from different angles are discussed in detail.2. Concurrent Design of multiple state machines is investigated. When the scale is quite large or the timing is very complicated, the circuit being designed can be reasonably divided into several parts, so each state machine may control corresponding division raising the efficiency of the circuit. This technology is especially suitable for bus interface circuit.3. Metastability and full/empty symbol usually occurring to asynchronous FIFO are also investigated, and a preferable modification come up.4. An approach to test bench is discussed. The test bench program is a virtual PCI system, which comprise the Microblaze model established from Xilinx EDK and also the PCI/PCI-X model from Synopsys company. Function level or gate level simulation can be done on this test bench.5. The PCI add-in card and the testing program are introduced.