Research On Electrostatic Discharge Protection Design Based On 40nm Process Circuit Module

Along with the development of the modern integrated circuit(IC), the process characteristic size is more and more smaller, gate oxide is more and more thiner, the operation voltage is more and more lower, the operation frequnce is more and more higher, the integrate rate is also more and more higher, the cost is getting lower and lower as well as lots of the advanced technology are used. All of those factors result the robustness of ESD to get lower and lower. However, static electricty will not decrease because of those changes.so that it is especially important to research the deep submicro CMOS IC ESD prevention.This paper introduces the basic concept of the electrostatic discharge phenomena, its application and the impact of CMOS integrated circuits at first, and then describes the ESD model, the industry standards and electrostatic discharge test of knowledge, and then introduce in detail the popular protective devices and common electrostatic protective circuits, further more, refer to the concept of whole chip ESD design. Based on SMIC advanced40nm CMOS process, by using the I/O, PLL and ADC module etc. as example, this paper has adopted the key ESD protective devices and the critical layout design to illuminate the importance of optimizing ESD design of each moudle. Those modules are in a MPW(Multi-Project Wafer). After encapsulated, the whole chip is tested in RE (Reliability Engineering) lab of SMIC by Thermo KeyTek ZAPMASTER Test System. The ESD threshold voltage of the optimized module is better than before. This paper demonstrates optimized designs of PLL module and ADC module, which have improved ESD performance significantly in customer chips.