Design And Implementation Of FPGA Interconnection Embedded In SOPC Test Methodology

Under the trend of higher and higher chip integration,FPGA companies began to embed the chip in the processor system,and So C FPGA is exactly the chip product born under this trend.So C FPGA is also called SOPC(System-on-a-Programmable-Chip),which can program the system on chip.Generally,the FPGA must be configured to a specific function before performing function and parameter testing during the test.Therefore,the FPGA must be able to quickly load the configuration code stream during the test.In order to configure part of the FPGA at the same time as the processor system is started,the So C FPGA eliminates the Select Map interface that is commonly used to configure test codes compared to traditional FPGAs,and adopts the code stream loading method of memory interface configuration,which is starting for testing.Simultaneously with the configuration,the efficiency is too low to meet the test requirements,which has become a key issue in So C-type FPGA testing.In order to solve the above problems,this topic selects the mainstream SOPC chip(Zynq-7000/XC7Z045)for the test plan design and verification.The Zynq-7000 series of chips embed ARM's Cortex-A9 dual-core processor system(Processing System,PS)into the Xilinx Programmable Logic(PL)system.This subject mainly tests the FPGA part of SOPC,that is,the connection resources of the PL part and some conventional electrical parameters.In order to realize the testing of So C FPGA connection resources,this subject mainly did the following research:(1)Research on the architecture and configuration method of So C FPGA,and refer to the traditional FPGA testing method,design the code stream loading scheme for So C FPGA.(2)Research the structure and test method of FPGA connection resources.Aiming at the structure of the metal connection resources of the Zynq7000 chip,design a deterministic connection resource test method with less configuration times and higher coverage.(3)Optimize the test process to form a test plan for So C FPGA.Finally,through the development of the XC7Z045 startup program,the chip successfully selected the configuration code stream in the SD Card to load through the ATE,as well as the double line and quadruple line traversal test and part of the conventional electrical parameter test.The specific test data was obtained,and the test time and the coverage of the double line and the quadruple line were analyzed,which verified the feasibility and effectiveness of the test scheme,and formed a test scheme for So C-type FPGA connection resources.