Design And Verification Of Fpga Configuration Control Circuit

As an important part of SOPC(System on Programmable Chip), FPGA(Field Programmable Gate Array) could realize the flexibility of SOPC with its various configurable logic resource and integrate different intellectual properties to expand the system. The development of FPGA abroad changes with each passing day, while the research on FPGA still has a long way to go at home. The self-reliance intellectual property FPGA becomes urgency for both national defenses and industry.The FPGA configuration circuit provides the interface between FPGA software and configurable logical hardware assuring the configuration data to be downloaded to the proper address. According to the analysis and abstract of the software and hardware interface, the configuration circuit of FPGA includes these parts: configuration interface, configuration registers, bus decoder interface, and configuration control circuit. And it has the features: reusable, multi-configuration mode and a fast configuration speed. The Specification for this design is 70MHz in both serial and parallel mode, 50MHz for both JTAG configuration and parallel readback, 33MHz for JTAG readback.Adopted the SMIC 0.18um-M technology, the RTL code and synthesis and STA of the configuration circuit which fulfills the SPEC are done. It is improved by the tape-out result that this design has the feature of rapid configuration speed, good reusage, various configuration modes and a high rate of successful configuration.