Research And Implementation Of FPGA IP Core Configuration Scheme In SOPC

The paper introduces the development and application of SOPC, the IP cores reuse technique firstly, after that, researches about the FPGA configuration flow and I2C data bus standard, and then, the paper puts forward a new configuration project that using the I2C bus configures the FPGA on a SOPC. This project makes use of the top-down design flow, designs the I2C bus interface (including master IP and slave IP) through verilog HDL. The soft and hardware connect mechanism design the connect logic between I2C IP core and FPGA configuration logic, FPGA configuration control logic. These courses of action set the I2C small IP into the FPGA IP. I2C presents to be a configure interface of FPGA IP. Then introduce the"FPGA+MCU+FLASH"SOPC system that was used in this paper. In order to verify the correctness of configure results, structure of configuration bit-stream and read-back bit-stream was analysis in simple terms. And on this basis, test the correctness of the research that configure and read-back the FPGA through I2C interface. This configuration project can carry out the configuration and read-back of FPGA. The production will provide a new method for FPGA IP configuration on SOPC.