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Research On Pixel Configuration Of High Definition 3D Screen Controlled By SOPC

Posted on:2017-01-02Degree:MasterType:Thesis
Country:ChinaCandidate:M LiuFull Text:PDF
GTID:2348330488981482Subject:Mechanical engineering
Abstract/Summary:PDF Full Text Request
Naked-eye 3D display technology can get rid of the bound resulted by glasses and provide a naked-eye 3D video sensation to the user, it can be applied to high definition display, monitor, portable mobile devices, vehicle display and other occasions, and it has huge market value and development prospects. High definition multimedia interface HDMI is the most widely used in the field of audio and video interface standard, its long distance without loss transmission, high data transmission speed and other features can be used for the video data transmission of naked-eye 3D device. In this paper, we use FPGA to realize the pixel configuration of high definition 3D screen with HDMI interface, the main research work is as follows:(1)Time sequence analysis and control technology of small screen LCD. Using FPGA to achieve precise control of LCD timing, through the control of horizontal synchronization signals, frame synchronization signals and pixel clock signal to realize the precise written of pixel data.(2)Circuit design and drawing of PCB board. After a thorough analysis of the HDMI transmission principle and stereo image features, proposed a HDMI HD display program based on low cost FPGA, selected chips and devices, designed the circuit schematic diagram and PCB layout of system, then weld and debugged the circuit board.(3)SOPC system design and software development based on HDMI interface. FPGA as the core of the design system, responsible for the completion of the output data’s processing, processed data transmitted through the HDMI cable to the display device, data processing matched the display device can realize stereoscopic display effect. Logic design by Nios II soft core processor, first constructed HDMI SOPC system and configuration required external digital circuits, and then write Nios II processor program.(4)Experiment and debugging. Send color data, pattern, high-definition image data and stereo data to high-definition screen with HDMI to verify the accuracy of the design in the process of system debugging.By working on LCD timing analysis, circuit design of HDMI high speed transmission, circuit board drawing and logic design, we completed the pixel configuration of high definition 3D screen, realized the HDMI display of high definition 3D screen and the separation, cache and fusion of left and right format stereo image. System architecture and logic implementation proposed in this paper can provide technical basis for the exploration and application of 3D equipment.
Keywords/Search Tags:Naked-eye 3D display technology, Stereo image, FPGA, Nios II, HDMI, Pixel configuration
PDF Full Text Request
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