Design Of Acquisition And Storage Module Of 8 Channels And 12bits Resolution

High speed,high-resolution,multi-channel acquisition system is very important for scientific research in various fields,and it is widely used in such scenes as seismic detection,pulse capture,burst test and so on.In view of the importance of high-speed and high-resolution multi-channel data acquisition system,this paper focuses on the design of a data acquisition and storage module,which has eight channels,12 bit resolution and2.5GSPS sampling rate.This paper show the design content of the module through the system design,hardware circuit design and FPGA logic design.In the design of the system scheme,this paper focuses on the main performance indicators of the module,combined with the chip characteristics of different suppliers in the market,trade-offs in performance and cost,and determines the analog-to-digital conversion,control and processing,deep storage and clock scheme of the module.In the chapter of hardware circuit design,firstly,the interface of ADC,FPGA and DDR3 memory is analyzed from the aspects of impedance matching and level compatibility,and the corresponding circuit design is completed.Then,according to the phase noise model of PLL,the simulation analysis and circuit design of the off chip loop filter are completed.Finally,in order to meet the different power requirements of each device in the module,the LDO and switching power supply are used to build the power supply circuit of the module.FPGA logic design mainly analyzes the acquisition process of the system based on trigger.Through the design of ADC data receiving module,on-chip memory module and deep memory module,completes the acquisition and storage of waveform data,and transmits the waveform data to the backend through SRIO data transmission module.For the data acquisition system using multiple JESD204 B interface ADC,the traditional synchronization method based on deterministic delay not only has high complexity,but also can only eliminate the transmission time difference from the transmitter to the receiver.There is no clear solution to the channel asynchrony caused by the unequal length of transmission line,the inconsistency of analog channel and clock skew such factors from the front end of ADC.Therefore,this paper innovatively proposes a multi-channel data synchronization and correcting method based on time stamp.By deploying the time stamp function of ADC and adjusting the output delay of clock chip,each channel data stream received by FPGA starts at the same time,and the delay between any two channels is less than 25 ps.Then,a control signal timing adjustment method is introduced to ensure the synchronization of waveform data storage and transmission of multiple sub modules.Finally,aiming at the problem of random offset of trigger point caused by insertion of elastic buffer in JESD204 B transmission and dynamic delay FIFO in time stamp function,a dynamic correction method of trigger point offset is proposed.Through the test and verification of the system bandwidth,the highest real-time sampling rate,the significant bits,the synchronization accuracy and the storage depth,it is proved that the data acquisition and storage module designed in this paper meets the index requirements,and achieves the research goal of this paper.