Multi-channel Gsps High-speed Data Acquisition Card Design

With the development of information technology,the frequency bandwidth of analog signal is getting higher and higher.In the field of modem electronic information,high-frequency signal generated by radar,sonar,nuclear detectors and other instruments is generally up to 100 MHz or even GHz.The acquisition of these high frequency signal requires higher sampling rate and higher accuracy.A multi-channel Gsps high-speed data acquisition card is designed in this paper.The data acquisition card uses 10bit 5Gsps TIADC for multi-channel sampling.It uses a highly scalable FMC interface to design a daughter-and-mother board structure,uses FPGA as the logic control core,and uses DDR3 memory and Gigabit Ethernet to realize data storage.The data acquisition daughterboard is designed with two schemes:one can achieve four channels of optional input with a single ADC,its four-channel sampling rate can reach 1.25Gsps,and single-channel sampling rate can reach 5Gsps;one can achieve two channels optional input with two ADC,which mainly realizes the function of dual-channel 5Gsps,and tries to verify the design scheme of single-channel 10Gsps by interleaving two ADC.This paper focuses on high-speed TIADC to design two sets of data acquisition daughterboard.We design analog signal conditioning,ADC high-speed sampling,low-jitter(<150fs)high-speed sampling clock,high-speed synchronization circuit and other hardware modules.We also design DDR3 storage and Gigabit Ethernet transmission interface of the data processing motherboard around FPGA.The high-speed data receiving FPGAlogic based on source synchronization is designed for ADC high-speed sampling using the serial-to-parallel converter ISERDES with an IODELAY adjustable delay unit.For the single ADC data acquisition card,there is only one FPGA on the motherboard.Its internal logic also includes the SPI configuration of clock chip and ADC chip,data integration and trigger control,DDR3 interface control and Gigabit Ethernet interface control.For the dual ADC data acquisition card,there is an FPGA on each of daughterboard and motherboard.Therefore,some logic modules are migrated to daughterboard FPGA,and BRAM is added to cache 100Gbps high-speed data,and data transmission of two FPGAs is realized.Finally,the performance of the data acquisition card is tested.The PC software and MATLAB processing program are written as the test platform.The performance parameters of ADC are tested after correcting the channel mismatch error of ADC.The test results show that two sets of ADC acquisition daughterboard perform well in both static and dynamic performance:the typical value of effective bits ENOB is 8.56(100MHz)in the single ADC acquisition daghterboard under single-channel 5Gsps mode,and 8.01(100MHz)in the dual ADC acquisition daghterboard under dual-channel 5Gsps mode.The main work and innovations of this paper are as follows:(1)Two hardware schemes of multi-channel Gsps high-speed data acquisition card are designed.Around 10bit 5Gsps high-speed TIADC chip,the research focuses on analog signal conditioning,ADC high-speed sampling,low-jitter(<150fs)high-speed sampling clock,high-speed synchronous circuit and other modules.(2)The FPGA logic design of ADC high-speed data receiving,caching,storing,and uploading is completed.On the basis of completing the SPI configuration of clock chip and ADC chip,a high-speed data receiving module based on source synchronization is designed by using the serial-parallel converter ISERDES embedded with the IODELAY adjustable delay unit.The real-time cache of 100Gbps ultra-high data rate is realized by using on-chip BRAM.(3)The host computer test platform is designed and the ADC performance test is completed.The PC software and MATLAB processing program are written as test platform for testing.The results show that the static and dynamic performance of two sets of data acquisition daughterboards are good,and the typical values of the effective bits ENOB are 8.56 and 8.01,respectively.