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Research On Multi-sensor High-speed Synchronous Accelerometer

Posted on:2019-01-16Degree:MasterType:Thesis
Country:ChinaCandidate:S H YaoFull Text:PDF
GTID:2428330548463430Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
The vibration and impact of high-speed transportation and airdrop materials will harm the safety of skydiving personnel,valuable equipment and medical supplies.Therefore,it is necessary to accurately record the size and duration of the impact in order to analyze the relationship between safety and equipment safety..The single-channel acceleration measurement system is a device for recording and storing the impact and vibration information during airdrop or vehicle travel.In general,large-scale equipment needs to obtain impact force parameters in different parts,so it is necessary to use multiple single-channel accelerometers simultaneously.The above method has the problems of low measurement accuracy,inability to synchronize measurement data,and failure to obtain information such as the stress distribution of the entire equipment at the time of opening and landing and the fact that a large amount of data redundancy information cannot be effectively used,and therefore urgently needs to develop a multi-channel synchronous acceleration acquisition system.In response to the above requirements,this paper studied a multi-channel high-speed synchronous acceleration acquisition system.The system framework is composed of multi-channel synchronous data acquisition subordinate machine,USB-based upper and lower computer interface and host computer client analysis software.The multi-channel synchronous data acquisition slave is mainly composed of Altera FPGA architecture and peripheral circuits.Including the front-end hardware filter,FPGA-based design of multi-channel high-speed data synchronization acquisition module in parallel mode,FPGA storage module,control module,lower and upper computer communication module.The front-end hardware filter module is designed with a second-order low-pass Butterworth active filter circuit.The selection of the circuit parameters is discussed,and the rationality of parameter setting is experimentally studied.High-speed acquisition module,using state machine diagram method to design a scalable high-speed full-parallel program,combined with storage,control module design simulation and experimental demonstration.The upper and lower machines communicate information through the serial data interface protocol.The main functions of the client analysis software include data reading,data analysis,data erasure,and time setting.Data analysis includes functions such as display of raw data,display of data fusion,storage of picture information,and export of specified range data.The data analysis module designed the maximum and minimum filters to improve the accuracy of data analysis for high frequency noise in the sampling process.Through the slack variable method,the above filter design problem was described as a second-order cone programming standard form.Effective solution.Finally,through the simulation test,experimental verification,PC host software and joint debugging of hardware equipment and other technical means,it verifies that the system design achieves the expected design goals.
Keywords/Search Tags:FPGA multi-channel high-speed synchronization, data acquisition, Butterworth active filter, maximum and minimum filters
PDF Full Text Request
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