Research And Implementation Of Synchronous Self- Tuning Method For Multi-Device In Ultra-High Speed Data Acquisition System

With the rapid development of technology and the continuous advancement of electronic information technology,the complexity of electrical signals has become higher and higher.Therefore,higher requirements are placed on the design indicators of the acquisition system for observing electrical signals.As an important part of the data acquisition system,the digital oscilloscope needs to improve the real-time sampling rate,channel bandwidth and resolution of the core indicators.The core device that determines the real-time sampling rate of the system is the speed of an analog-to-digital converter(ADC),or an n-sample high-speed sampling rate ADC achieveing n times the sampling rate by means of time-parallel parallel sampling.High-speed data acquisition system.The domestic data acquisition chip manufacturing process is relatively backward,and in the short term,the speed of data acquisition cannot be improved by increasing the speed of the sampling chip.This paper starts with the time alternating parallel sampling technology,and deeply researches the parallel sampling technology to build a parallel sampling system to realize the ultra-high speed data acquisition system.The following contents are the main research of this paper:Firstly,the principle of time-interval parallel sampling system is studied in depth,and the overall scheme of ultra-high-speed multi-device parallel sampling system is analyzed in detail.The synchronization problem between multiple devices is analyzed.The feasible solution that synchronization problem of multi-device acquisition and multi-device storage synchronization are respectively proposed.Design data processing circuit board,design high-speed low-jitter multi-phase sampling clock,design trigger circuit with frequency division controllable function,design ADC synchronous reset control circuit,etc.Secondly,the common synchronous reset correction scheme and the synchronous reset signal design principle in parallel sampling are analyzed.The multi-ADC synchronous reset signal control module is designed.The multi-FPGA multi-core ADC data receiving scheme is designed.The multi-ADC sampling process is deeply studied.The synchronization problem that exists in the synchronization parameter in the synchronization control.A single ADC data receiving synchronization scheme and correction algorithm and multi-ADC sampling synchronization scheme and correction algorithm are proposed for the system.Third,a multi-FPGA(Field-Programmable Gate Array)data transmission and reception scheme are designed,the data storage synchronization problem among multiple FPGAs is analyzed,a multi-device storage link solution is designed,based on first-in first-out(FIFO)the storage unit reads and writes the signal delay of the data storage synchronization scheme and an automatic correction algorithm are designed.A multichannel data splitting solution is designed.Study the synchronization delay between multiple channels and design an inter-channel synchronization delay correction scheme.Through the debugging of each module of the system and the performance test of the whole machine,the synchronous correction control of the system has reached the design goal,and the synchronous automatic correction of the ultra-high speed parallel data acquisition system is realized.