A 16-bit Successive Approximation ADC Design

Successive approximation(SAR)ADCs are widely used in low-power consumption applications because of the fewer analog modules.SAR ADCs usually use capacitors to form DAC modules,which can fully meet low-precision and medium-precision applications.However,in high-precision applications,the mismatch of capacitors can not be ignored.At the same time,the DAC module requires more capacitors as the number of bits increases.Therefore,the primary problem to be solved in the research of high-precision SAR ADC is how to reduce the power consumption while ensuring its own accuracy.This article designs a 16-bit 1MS/s high-precision SAR ADC based on the 0.13?m BCD process.In order to solve the power consumption problem,this paper proposes a two-step predictive tracking SAR ADC.By introducing an auxiliary ADC in the SAR ADC,the high-order code value is predicted,thereby reducing the power consumption of the high-order large capacitor in the SAR ADC.Another benefit of the prediction is that the input swing of the comparator is reduced,and the requirement for the power supply voltage of the comparator is relaxed.A low-voltage domain comparator can be used to further reduce the overall power consumption.This paper analyzes and quantifies every non-ideal factor in the proposed two-step predictive tracking SAR ADC architecture.Combining the principle of non-binary coding,the corresponding integer non-binary coding is designed to provide sufficient redundancy to compensate for errors caused by non-ideal factors.After that,a digital calibration based on digital dither is proposed in combination with the specific architecture of SAR ADC.The digital calibration uses the characteristics of auxiliary ADC prediction to add digital disturbance before the predicted codes is loaded to the 16-bit main ADC,so that the 16-bit main ADC can compare with the same input signal to generate two sets of output codes.Then the actual capacitance weight value is solved according to an iterative algorithm.Since the digital calibration does not require additional analog circuits,and combined with the two-step predictive tracking SAR ADC architecture,the time required for quantization twice can be reduced.Thereby the calibration algorithm reduce the requirements for analog circuits.The 16-bit two-step SAR ADC architecture and calibration algorithm were simulated and verified by MATLAB.For the design and simulation of each circuit module the two-step predictive tracking SAR ADC,the selection of the potential capacitance value is determined through the analysis of the noise.In terms of the comparator,comparators in different voltage domains are designed to meet the requirements of auxiliary ADC and 16-bit main ADC.This article introduces the overall timing of digital logic and the construction of switch logic.Finally,the overall simulation of the two-step predictive tracking SAR ADC is carried out.The overall reference voltage is 5V.In terms of power consumption,the main ADC comparator power supply voltage only needs 1.5V,its power consumption is reduced by 3.4 times,and 7 quantization cycles are reduced when digital correction is turned on;the switching power consumption of MSB capacitors is also reduced by 6 times.In the case of considering the transient noise,the ENOB is 14.02bits when the digital calibration is used.