Research On The Method By Using Hidden Markov Model To Control The Testing Temperature Of Integrated Circuits

With the continuous changes in integrated circuit manufacturing processes and the demand for test efficiency and reliability,new challenges have been brought to the integrated circuit industry in terms of testing.How to improve the efficiency of chips during testing and reduce the cost of testing in chip production,became an important part of the integrated circuit industry.The ever-increasing amount of test data and the escalating complexity of circuit functions have caused a rise in the test temperature and an increase in power consumption.Consequently,the temperature rise will cause major damage to the chip.With the increasing of test data,there are higher requirements for the storage capacity,I/O channel number,and frequency of automatic test equipment.At the same time,the existing chip test schemes are no longer able to face more complex circuit structures.These problems directly lead to reducing the test efficiency,as well as increasing test cost.Therefore,the search and improvement of integrated circuit test methods have important theoretical and practical value for solving these problems.This dissertation starts from the test vector,and improves the efficiency of the chip in the test by reordering the test vector.The model and the formula of power consumption and temperature,the problems of excessive fluctuation of test temperature that may cause damage to the chip,are studied and analyzed in this dissertation.And a hidden Markov model is proposed to process the test vector,provide a variety of sorting schemes,and evaluate the probability of each scheme to minimize the temperature change.The optimal sorting scheme is tested in the fourth chapter,and the test power consumption and test temperature are calculated according to the test characteristics and circuit structure.Moreover,the sorting method can be combined with fault testing to reduce the test temperature without significantly increasing the test time.The sorting method is used to conduct simulation experiments on ISCAS 89 and ITC99 standard circuits.The final experimental results show that the use of Hidden Markov Models for the test vectors has effectively controlled the temperature of the circuit under test and reduce the test time.Controlling the temperature has contributed to avoiding the chip damage,while reducing the testing time has improved the testing efficiency of the chip,and reduced the cost of chip testing.The reordering of test vectors is an optimization of IC test method based on statistical model,that is,statistical model is introduced into the reordering of test vectors,and hidden Markov model is used to process the test vectors.Considering the power consumption and temperature of the chip test,the previous test process is optimized,and the temperature is controlled by sorting the test vectors.At the same time,this sort method can also be combined with fault sort on the basis of temperature control.On the basis of not significantly increasing the time,the temperature of the test can be controlled,so that the chip test can be completed better and faster,and the cost of chip test can be saved.