Research On Adaptive Testing For Test Vector Reordering In Integrated Circuit

With the rapid development of integrated circuit(IC)design and manufacturing technology,the number of transistors integrated on a single chip has reached 10 billion.The complexity and scale of IC have been greatly improved.The increasing amount of test data and the complexity of circuit functionsdirectly lead to the decrease of test efficiency and the increase of test difficulty.The huge amount of test data places higher requirements on the storage performance,number of I/O channels and frequency of the automatic test equipment.At the same time,new test methods must be developed to adapt to the more complex circuit structures.These problems directly lead to the increase of test cost,so the research on IC test methods has great theoretical significance and practical value.In Chapter 1,several methods for improving test efficiency were introduced,as well as the relevant background and recent research situation at home and abroad of adaptive testing methods.In Chapter 2,started with the test vector reordering in the adaptive testing,the problems of large test data and low test efficiency were analyzed.A test vector reordering method based on the Gamma distributionwas proposed.A probability model based on the Gamma distribution was established for the probability of each test vector hitting the fault.During the test,the test data was collected and added to the sample space,the parameters of probability model were dynamically updated,and the test vectors were reordered synchronously.The results show that the reordered test set has higher test quality.In Chapter 3,on the basis of test vector ordering,test type ordering was combined.The effect of test vector and test type ordering on test efficiency was studied.A hierarchical dynamic adjustment method for IC was proposed.Using the fault detection data collected from the test equipment,a Bayesian probability model was established to calculate the probability when the number of hitting faults of each test vector is greater than 0.According to the probability of hitting fault,the test types and test vectors were reordered dynamically.Using the optimized test process to test can effectively reduce the test time of faulty circuit.The simulation experiments are carried out on ISCAS 89 and ITC99,and the experimental results show that the two methods in this thesiscan effectively shorten the test time of faulty circuit.At the same time,experiments are performed on actual ICs,the results show that the two methods in this thesisis suitable for both digital circuit and analog circuit,and have strong generality.Moreover,does not increase the hardware overhead,and can be combined with traditional testing methods.