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Radar IF Target Echo Simulator

Posted on:2021-07-03Degree:MasterType:Thesis
Country:ChinaCandidate:Q W XuFull Text:PDF
GTID:2518306512978509Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Radar Intermediate-Frequency Target Echo Simulator is used to simulate target echo signals at intermediate frequency(IF)level in real time.It plays an important role in the development,commissioning,training and maintenance of radar.According to the actual appication requirements,this paper designs and implements a kind of Radar IF Target Echo Simulator based on FPGA,which is capable of simulating target echo signals with distance,radial velocity and angle information in real time.In order to restore the influence of environment on the radar target echo signals,noise and clutter are also simulated.The research and implementation of Radar IF Target Echo Simulator in this paper is carried out in the order of scheme design and simulation,hardware circuit design,FPGA software implementation,and system debugging.In the scheme design and simulation stage,the scheme and workflow of the simulator system are developed according to the task requirements.Then the radar target echo model is analyzed,the target echo expression is derived,and the target echo is simulated and verified in Matlab.Finally,several radar noise and clutter models are compared and analyzed through simulation.In the hardware circuit design stage,the scheme of the simulator’s hardware board circuit is given,and the board is divided into six circuit modules: FPGA module,power module,clock module,interface module,mermory module and DAC module.According to the requirements of each module,the chip selection and schematic drawing are completed.In the FPGA software implementation stage,the top module divides the simulator software system into eight functional modules,which are clock and reset module,chip configuration module,interface module,DAC output module,calibration module,echo generation module,noise and clutter module,and embedded softcore module.Then the Verilog HDL program is written to generate radar target echo according to the functional requirements of each module.Finally,the FreeRTOS reat-time operating system and lwip protocol stack are transplanted on the Micro Blaze to complete the UDP package communication and the calculation of the target track.In the system debugging stage,the whole simulator system is debugged,and the radar intermediate frequency target echo siganl generated by the simulator is observed through the oscilloscope and spectrum analyzer.The echo signal is verified that the target echo signal generated can accurately reflect the information of the target.
Keywords/Search Tags:Radar Target Echo Simulator, FPGA, Noise and Clutter Simulation
PDF Full Text Request
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