Design And Implementation Of RSA Fast Encryption IP Core Based On FPGA

With the continuous advancement and development of the process of information globalization,the frequent leakage of information makes information security one of the hot issues that people pay close attention to and need to be solved urgently.RSA encryption is a safer and widely used public key cryptography algorithm,the core of which is modular exponentiation.With the continuous improvement of computer computing power,the modular length of RSA algorithm increases correspondingly for security reasons.Thus the rapid implementation of RSA encryption algorithm has vital practical significance considering the corresponding increase in encryption and decryption time.The hardware implementation of RSA encryption algorithm has obvious advantages compared with software implementation.After studying the improvement scheme of RSA algorithm,the realization of 1024-bit RSA IP core by hardware verifies the feasibility of the improvement scheme.This paper first studies the principle and implementation of RSA cryptosystem,compares and analyzes several different modular exponentiation and modular multiplication algorithms,and studies a set of improved RSA algorithm.On the one hand,in the selection and improvement of modular exponentiation operation,this scheme adopts the L-R high binary method as a whole,which reduces the number of loop iterations of modular multiplication operations;and uses R-L binary arithmetic in data pre-calculation,which is convenient for hardware parallel implementation.When the power exponent has the same probability of 0and 1,the improved modular exponentiation scheme can reduce the number of modular multiplications by about 18.0% compared with the binary scheme.On the other hand,in the selection and improvement of modular multiplication operations,the Montgomery modular multiplication algorithm is used to avoid division by shifting;the SMM optimization algorithm is used to effectively reduce the calculation amount of modular multiplication operations;In data preprocessing,two ordinary modular multiplication modules are used to map multipliers from integer domain to Montgomery domain.The improved modular multiplication scheme not only reduces the amount of computation,but also is suitable for hardware implementation and optimization.The efficiency of RSA algorithm is improved through the above two improvements.Secondly,based on the improved RSA algorithm,a 1024-bit RSA IP core was realized with the help of FPGA platform.There are two improvements in hardware implementation:on the one hand,certain hardware resources are saved by the small bit width data defined by width optimization and the operation efficiency is improved by the big bit width.On the other hand,the parallel pipeline optimization is used for the loops in modular exponentiation module and modular multiplication module.The delay is reduced by about 15.1%,and the clock frequency is increased by about 17.8%,which improves the performance of RSA IP core.The Vivado HLS is adopted to model,simulate and test different functional modules and the IP core is integrated and packaged after verifying the correctness.The Vivado is adopted to test the performance of IP verification after instantiation.The correct encryption and decryption results of RSA IP core verifiy the feasibility of the improved algorithm.Under 100 MHz clock frequency,the encryption speed of IP core is about 21.2 ms / time,and the decryption speed is about 31.4 ms / time,with excellent performance.