Design Of Encryption IP Core Based On IPSec Protocal And FPGA Implementation

With the increasing number of Internet users, the address space of IPv4 (Internet Protocol Version 4) has been increased inadequate, IPv6 (Internet Protocol Version 6), as a new-generation network protocol, will soon enter the large-scale application stage. In the face of complicated network environment, network, only based on IPv6 Protocol itself, will exist a huge security risk. Therefore, IETF (Internet Engineering Task Force) stipulates that IPv6 must support IPSec (Internet Protocol Security) protocol in order to ensure network layer data security. The security of IPSec relys on intensive algorithm data computation, but its software implementation efficiency is low. So this thesis puts forward a design of encryption IP core based on IPSec protocol. This design, without taking up lots of CPU resources, applies hardware circuit implementation, which greatly improves work efficiency and has great significance to the study of IPv6 network security technology.Firstly, This thesis does a series of research and analysis on IPSec protocol, describes the system hardware design of IPSec protocol and the working conditions of the system. Then, this thesis designs hardware system architecture of encryption IP core, partitions modules and sets the data interface of IP core. Detailed elaboration is also given to the functions of the key module, structure, data packet format and circuit design, etc. The Verilog hardware description language is used to design the RTL (Register Transfer Level) of each module, and the function simulation is completed, this design of encryption IP core support three kinds of algorithm model:AES-CBC,3DES-CBC and NULL. AES-CBC algorithm support three kinds of secret key whose lengths are 128 bit,192 bit, and 256 bit. It can analyze the IPv6 datagram and complete IPSec encryption and decryption processing under the transmission mode and the tunnel mode, which has a certain timeliness and innovation.Finally, verification platform is set up. The verification of encryption IP core is performed on Xilinx XUPV5-LX110T FPGA(Field Programmable Gate Array) development board, and the output is printed on the PC program interface, which realizes the various function.The data width of the whole hardware system is 32bit, and the system master clock can reach 150MHz, which achieves the desired performance index.The design can be directly applied to IPSec protocol security processor engineering practice based on IPv6, can also be applied to those safety engineering projects involving code chip, which greatly shorten the project development cycle and has important practical significance for engineering.