Research And Design On A 2048 Bits RSA Co-processor IP Core

In this thesis, a RSA co-processor IP core with the key length of 2048 was investigated. First of all, variable commonly used algorithm and architecture of RSA co-processor were analyzed and compared in order to bring forward a new architecture based on systolic array and Montgomery algorithm. RSA co-processor with the length of 2048 bits has 4 times the calculation and complexity compared with the traditional 1024 bits co-processor. So to realize the 2048 bits RSA co-processor with low hardware complexity and high performance is the bottle neck.We presented a serial-time-division-multiplex-non-interleave architecture for the new 2048 bits RSA co-processor, based on the systolic implementation. The gate counts and area were significantly reduced by share the same systolic array in both multiplication modular and square modular, which was improved by the results from Synopsys Design Compiler. The dynamic power was also reduced compared with the paralle-time-division-multiplex-interleave with not very large degression of the speed.