Configurable Encryption And Decryption Processor Based On RSA/ECC Algorithm

The algorithms of RSA and ECC are the cornerstone of asymmetric encryption technology,they are safe representative algorithms in asymmetric system.They not only have high security feature,but also provide functions such as digital signature and identity authentication.Nowadays,high security is urgently needed,and the bit width becomes larger and larger.Thus,the demand of complex calculations is getting more urgent.However,software implementation cannot meet the requirement of high speed.Therefore,the implementation of RSA and ECC is of great significance.The coprocessors of RSA and ECC are implemented in this paper.The part above the protocol layer is implemented by software,and core operations are implemented by ASIC.This paper first analyzes various algorithms of RSA and ECC,and chooses algorithms that are suitable for hardware implementation.For the implementation of RSA,the modular multiplication layer is implemented by an optimized Montgomery algorithm,and the modular exponentiation level is implemented by a binary expansion algorithm.As for ECC,the elliptic curve uses the Koblitz-233 recommended by NIST on the binary field GF(2n).The top layer is implemented by the Montgomery algorithm on the projected coordinate system.The inverse algorithm on the finite field is optimized by the Fermat Theorem,which achieves the inverse by calling basic operations on the binary field.In the process,the hardware resources are optimized to improve the performance significantly.Besides,all attacks are carefully considered and the coprocessors have good anti-bypass attack features.In the process of implementation,this paper first designs the overall framework based on the original algorithm and optimizes the hardware structure,then completes the RTL-level code.Secondly,the configuration tool designed by this paper can be used to configure bit width,algorithm,and parallelism for different requirements.Based on the idea of Reconfigurable Computing(RC),it is divided into static configurable and dynamically configurable structures.For static configurable structures,it is accomplished by the configuration tool.For dynamic configurable structures,the large bit width can be backward compatible with the small bit width,which greatly reduces the cost of resources.Therefore,the entire design is highly flexible.In the implementation process,the design aims to meet the different requirements of different applications,it can directly generate Verilog code that has been verified by the configuration tool,which greatly reduces design time and improves product competitiveness.In this paper,various structures of RSA and ECC are verified.The simulation diagrams of various configurations are listed,and the results for each simulation diagram are analyzed.Based on TSMC 28 ns process,this paper use DC as the tool to compile,and this paper also analyzes the compiled results of different configurations.For example,the master frequency of ECC is 2.38 GHz with full parallel configuration,and the speed can reach4000000 scalar multiplications per second.When the RSA configuration tool is set to1024 bit R-L scanning method base on full serial Radix-2 Montgomery,the gate resources are 21 k gates,the master clock frequency is 2.5GHz,36,000 operations per second can be achieved,and a scalar multiplication only takes 27?s,which reaches the initial design goal.