Hardware Design Of Encryption/decryption And Digital Signature Verification Based On SM2

With the rapid development of information technology,the requirements of information security has become more and more stringent.In order to get rid of excessive dependence on foreign technology and products.And strengthen independent industry information security,the security chips based on national encryption algorithms emerge.The SM2 national encryption algorithms has great advantages in performance,encryption key's strength and storage space among kinds of asymmetric public key cryptogram algorithms.Therefore,it is of great significance to study the hardware implementation of SM2 algorithm.This thesis implements the hardware design of encryption,decryption and digital signature verification based on the SM2 algorithm.The main tasks of the thesis are as follows:The system design scheme of SM2 encryption/decryption and digital signature verification hardware circuit is designed,including system composition structure,module division,the definition of I/O interface and memory address mapping.The key modules of SM2 encryption/decryption and digital signature verification hardware circuit is designed.Among them,the design of SM2 process control module includes the state machine that controls the main process,encryption process,decryption process and digital signature verification process,as well as the state machine of the K-point calculation process and SM3?ctrl process used in the encryption,decryption and digital signature verification.The task management module manages the execution of reusable SM2 operations and basic arithmetic operations through a task-step mechanism,and efficiently completes the data operation required for encryption,decryption and digital signature verification;The Multiple-word Radix-2 Montgomery Multiplication(MWR2MM)module adopts the word-based Montgomery algorithm to implement the modular exponentiation unit.The pipeline design method is used in the MWR2 MM module,and the configurable pipeline stages(1-7 stages)are designed to meet the trade-off requirements of for the chip area(hardware overhead)and the speed of encryption,decryption and digital signature verification(data throughput)for different customers.The verification plan for SM2 encryption/decryption and digital signature verification hardware circuits was developed,while the simulation verification platform was built based on Makefile scripts,System Verilog language and UVM general verification methodology to verify the function of the hardware design.The simulation results and system verification coverage show the effectiveness of the hardware design.