Improvement Of Rsa Crypitography Algorithm And Implemention Of ITS IP Core

As the most widely used public-key encryption algorithm, RSA plays an important role in the field of information security with applications of the data encryption and digital signature. With the rapid development of computer technology, the standard length of RSA keys becomes bigger and bigger, bringing greater challenge on the implementation of RSA algorithm. At present, there are mainly two methods of implementation of RSA algorithm—software and hardware implementation. The software one has applied to all kinds of Internet transmission protocol, to guarantee the network security; Compared with traditional software encryption, hardware encryption is faster, has higher stability and compatibility, better security and many other advantages. As modern IC technology forward, in particular, small-scale electronic equipments such as IC card、USB Key, get more and more opportunities applying in the field of electronic commerce; So, embedding the RSA coprocessor into these small hardware will be of great realistic significance today with the highly developed electronic commerce.In order to realize the low-end RSA implementation suitable for small hardware, an optimal solution of comprehensive performance is needed to be found. This paper firstly analyzes the principle of RSA algorithm and its implementation algorithm in theory, and then make the improvement based that. RL binary scanning has chosen to be the implementation mode of modular exponentiation, and improvement named IIFIOS has made to FIOS—one of classic improved implementions of Montgomery algorithm, which is superior to CIOS—originally considered to be Montgomery implemention method of optimal comprehensive performance—in time and space complexity. At thesame time, considering the balance of area of the hardware implementation andcomprehensive performance, make improvement on parameters of modularmultiplication and modular square.Based on the improved algorithm, RSA modular multiplication andmodular exponentiation has been realized on VS platform in C language, tocomplete the RSA software modeling. According to the softwareimplementation and its result contrast, correctness of the algorithm has beencompleted, and improvement on performance of RSA implementation has beenproved on the software level, which laids the foundation for IP core ofhardware implementation later.For the design of RSA IP core, considering of low-cost andhigh-performance,32-bit as basic data width of the process, the algorithm inoptimization of ideas has effectively implemented, and improved IIFIOSmontgomery algorithm for pipeline structure has been realized in hardwareimplementation. Meanwhile, some optimization strategy has been made, such asindependence and reuse of modules, data path optimization, storage mappingstrategy of IP, etc. RSA IP core has passed the simulation，the FPGAverification test and ASIC synthesis. Under the100MHz clock, results showthat2048-bit modular speed is about4times per second, and1024-bit one isabout36.7times per second; in gsmc0.13um technology, the gates count of IPcore is76k, while the one of Sram is46k taking60percent of the whole IP,which is a good performance and has advantages with other designs.The improved RSA algorithm has certain advantages, both in softwarerealization and hardware implemention based on IP core.