Research And Design Of A Low-Power Sigma-Delta Modulator

With the rapid development of emerging fields such as 5G,artificial intelligence,electronic vehicles,and medical instruments,the demand for Analog-to-Digital converters is also growing rapidly,and different requirements for signal processing in different application scenarios are promoting the update and iteration of Analog-to-Digital converters.As a kind of Analog-to-Digital converter,Sigma-Delta ADC uses oversampling and noise shaping technologies in its modulator part so that it can obtain high accuracy,which makes it become a hotspot for researchers.To obtain higher accuracy,Siga-Delta modulator structure gradually becomes more complex,and circuit power consumption is also increasing.In this thesis,a single-loop second-order 6-bits quantizer Sigma-Delta modulator circuit with high accuracy and low power consumption is designed,and three improved methods are proposed for improved accuracy and reduced power consumption.(1)There are a large number of switching circuits in the Sigma-Delta modulator.However,traditional gate-voltage bootstrap sampling switches have non-ideal factors,such as parasitic capacitance charge sharing effect in the bootstrap path,channel charge injection during MOS transistor turn-on and turn-off,and clock feed-through due to parasitic capacitance.These factors make the modulator circuit accuracy limited.To solve the abovementioned problems,an improved sampling switch is proposed.Compared with the traditional gate voltage bootstrap sampling switch structure,this new structure changes the control signal position of the bootstrap path switch,reduces the parasitic capacitance of the switch gate level,weakens the channel charge injection,charge sharing effect and clock feed-through phenomenon,and improves the accuracy of the modulator circuit.Besides,the improved sampling switch also eliminates the voltage multiplication circuit of the traditional structure and reduces the power consumption of the circuit.(2)Due to the manufacturing deviation of the circuit,the multi-bit quantizer in the Sigma-Delta modulator introduces an offset voltage during operation,resulting in overload during the modulator integration process,which seriously affects its accuracy.To tackle these problems,the method of adding an extended capacitor array to the quantizer circuit to sample,quantize,and cancel the offset voltage is adopted to realize the self-correction of the quantizer offset voltage and improve the accuracy of the Sigma-Delta modulator circuit.(3)Design a new Sigma-Delta modulator circuit structure based on SAR quantization to complete high-precision and low-power noise modulation.The new circuit structure replaces the traditional sampling switch with an improved sampling switch to improve the sampling accuracy of the modulator and reduce the power consumption of the modulator.The successive approximation quantizer with offset self-correction technology is used to replace the Flash structure quantizer in the traditional modulator circuit,and the integration method of the successive approximation quantizer and the modulator is given,compared with the multi-bit Flash structure quantizer,the successive approximation structure quantizer only needs a comparator to complete the multi-bit quantization work,thereby greatly reducing the power consumption of the Sigma-Delta modulator circuit.Under the Cadence platform,the overall circuit and layout design of the Sigma-Delta modulator are completed by using the DONGBU 0.18μm CMOS process,and the core layout size is 1213μm ×689μm.Simulation results show that under the condition of 5V power supply voltage,the quiescent power consumption of the modulator is only 20.71 m W,the sampling frequency is 5.12 MHz,and the effective number of bits within 5KHz signal bandwidth reaches 19.2 bits,which basically meets the design requirements.