A High-Linear Digital-to-Phase Converter

With the advent of the big data era,high-speed serial links(Ser Des)have attracted widespread attention due to their low cost and strong antiinterference.Digital-to-Phase Converter(DPC)is one of the important clock modules,and its linearity determines the jitter performance of the receiver.Therefore,research on DPC with high linearity is of great significance to suppress jitter and reduce the bit error rate of serial communication systems.This thesis first introduces the working principle and architecture of DPC,and elaborates its system specifications.Then,relevant sub-modules of DPC are introduced,including a duty cycle corrector,a multiphase clock generator and a phase interpolator.Through a digital-analog mixed negative feedback loop,the duty cycle corrector tunes the common mode point of the differential input clock,so that the duty cycle of the input clock can be adjusted.The multiphase clock generator is implemented by a DelayLocked Loop(DLL).Two sets of phase detectors are used to identify the phase difference.The phase detectors adjust the two sets of phase differences through a negative feedback loop in order to make the phase differences equal,which locks the DLL and generates a uniform multiphase clock.Phase interpolator is the core component of DPC.Focusing on the non-linearity of phase interpolator,this thesis first models the phase interpolator and expounds the relationship between non-linearity and circuit parameters through mathematical analysis.Then,the harmonic rejection technology and nonlinear weight interpolation technology are proposed to suppress harmonic nonlinearity and system nonlinearity.This design is a high linearity,low power DPC based on a CMOS 40 nm process.With the power supply voltage of 1.1V and the operating frequency of 4GHz,the differential nonlinearity is less than 0.17 LSB,the resolution is1.953 ps,and the power consumption of the DPC is 10.5mW.