| The simulation verification conducted by MATLAB is affected by the performance of the computer,and the efficiency is low,while the hardware accelerated simulation represented by FPGA is not suitable for different algorithm models due to its poor portability.In addition,simple theoretical research and off-line simulation are easy to produce problems that deviate from the reality or are partial.However,by connecting the physical objects to the system to replace the virtual model as much as possible,the simulation results are closer to the actual situation.At present,it has been widely used in the experimental research of the initial stage of system development in various research fields and the inspection process of styling equipment.By combining hardware testing and software evaluation,on the one hand,it solves the problems of abstraction of the system model in the pure digital offline simulation system,and the simplified model cannot effectively simulate the system.On the other hand,it also avoids the long development cycle of the system and the repetitive work.Reducing the system development costs and risks effectively.This subject proposes a system for fast verification of algorithm performance based on the combination of computer software and hardware,and verify the performance of different channel codec algorithms under the same platform framework.Under the design premise of following the principles of modularization,standardization,reliability and readability,the system is divided into two parts: computer softerware and hardware.The functions of each module are independent of each other.The modular structure is more suitable for the verification of the performance of different encode algorithms.Among them,the computer softerware realizes data generation,post-analysis and comparison of data,and system control work,while the hardware mainly realizes channel coding,modulation,noise,decision demodulation,channel decoding,parameter configuration,data download,data upload,error statistics and other functions.The computer softerware and the hardware communicate through the PCIe2.0 bus.After the user configures the simulation parameters,the command information is sent to the hardware through the register.The original information data and noise are transmitted to the hardware,and the data in the simulation process need to be cached for subsequent experiments or analysis.The DDR-based big data cache technology is used to implement data buffer scheduling.The data transmission rate can be greatly improved through the PCIe serial bus technology.When the host computer software side is configured with a 2-channel PCIe interface,the theoretical value can reach 16 GB / s.Finally,in order to be compatible with different encoding and decoding algorithms,the algorithm module of the lower computer system realizes a standardized design,and the synchronous control of the noise and the modulated symbol data can avoid the unnecessary error caused by the simulation process.In order to verify the integrity of the system,the RS(255,223),convolutional codes and puncturing recommended in the CCSDS standard are selected for testing.The test results show that the system designed this time can support the verification of the performance of different channel encoding and decoding algorithms,and each module The performance of the system and the overall performance of the system meet the design specifications.The user can control the system to perform data comparison and analysis,and view the simulation results.This solution can improve the verification efficiency of the performance of the channel codec algorithm,simplify user operations,and provide a reference solution for subsequent research on the performance of the channel codec algorithm. |
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