Ccsds Standard Plural Transform Domain Of Rs (255.223) Decoding Algorithm And Its Implementation

Nowadays, satellite communications have deeper space, higher data rate, more reliability and security, traditional digital communication can't meet the needs, so error correction technology is used to be the data communication. Comparing the error correction code with QPSK, kinds of error correction codes could get different code gain, it can get low BER in low SNR conditions. It means, with the same ground receive instrument, that the satellite could work in deeper space and more abominable environment. So error correction codes become the research focus of space electronics. There emerged some codes such as Reed-Solomon code and Turbo code. Comparing to kinds of codes, Reed-Solomon (RS) code shows great performance in correcting outburst error and random error. CCSDS (Consultant Committee of Space Data System) suggests that space communication adapts RS code in data link layer. RS code was adapted in our "DOUBLE STAR"exploration plan, but for the complexity of RS decoder, we used software to decode the RS code, so it can't guarantee real time communication. In our future plant exploration, there will be more far away and higher data rate(>150Mbps), so developing a hardware decoder is necessary. Because of the complexity of RS decode algorithm(based on finite field, GF), so firstly we researched kinds of RS decode algorithms, and promoted a complex number representation of GF element, then researched a rapid multiplexer of finite field, reduced the complexity of computation of GF, the result showed that it can greatly cut down the area of FPGA, and then decreased the decode delay; secondly, we researched the decoder's timing, to our best of our ability to pipeline the decoder, at the same time, the decoder must meet the needs of CCSDS, such as data synchronization, anti-disorder, and deinterleaving. To guarantee the real-time decode, these function must be implemented by hardware. Finally, the output of the decoder passed by the PCI bus ,then stored in computer's hard disk. We implemented the RS decoder based on FPGA, by EDA tools, develop the decoder within Top-Down design method, focused on decreasing the complexity of algorithm and pipelining the decoder. In our system design, we considered the signal...