The Design Of Key Blocks Of Analog Front-End

With the development of semiconductor process and circuit techniques,integrated circuits show a higher degree of integration and better performance,and play an indispensable role in wireless communication fields.In this thesis,a reconfigurable active low-pass filter with high out-of-band rejection and a 14-bit hybrid DAC are designed for analog front-end of asymmetric wireless communication.According to the requirement,a novel high out-of-band rejection low-pass filter with tunable bandwidth and programable gain is proposed.The proposed filter consists of a biquadratic Gm-C filter,a gain-boosting stage and a 5th-order elliptic filter.In the proposed filter,the variable gain is achieved by the biquadratic Gm-C filter and the gain-boosting stage,and the tunable bandwidth is achieved by capacitor arrays.And 5th-order elliptic filter is useful for improving the out-of-band rejection of overall filter.Besides,in order to achieve low power consumption,a fully differential common source stage with source degeneration is used as operational transconductance amplifiers in the circuit.The parameter optimization and layout design are finished.The pre-layout simulation and post-layout simulation are compared to illustrate the effect of layout on circuit performance.The proposed filter is implemented in TSMC 65nm CMOS process occupying 1.23mm2.The overall filter's power consumption is 4.6mW with 1.3-V and 2.5-V power supply.The post-layout simulation is as follows:the gain control range is from-20.5dB to 20.2dB;the bandwidth is tuned over a range of 1.030.5MHz;the minimum out-of-band rejection at twice bandwidth reaches 44.7dB;the Pin,1dB is-7.1dBm when gain is 9.9dB and bandwidth is 30.5MHz.This thesis proposes a 14-bit hybrid DAC for asymmetric wireless communication,which has been segmented into three parts:6-bit thermometer current steering structure,4-bit binary-weighted current steering structure and 4-bit equal current sources switched into an R-2R ladder structure.And the relationship between the relative standard error of current source and INL as well as DNL of binary-weighted current steering structure,thermometer current steering structure and segmented current steering structure is illustrated.Besides,it is illustrated that the requirement of gain of operational amplifier in output stage.Then,the key function module circuit such as bandgap circuit,V-I conversion circuit and unit current source circuit is designed.The parameter optimization and the layout design are finished,and the post-layout simulation of some module circuits and overall circuit are given.The proposed DAC is fabricated in SMIC 0.18 ?m BCD process.The active area is 0.754mm2 and the total power consumption is 40mW with a 5-V power supply.The post-layout simulation is as follows:DNL and INL are 0.41LSB and 0.62LSB,respectively;the settling time is 900.9ns;when sampling frequency is 1MHz and input signal frequency is 49.8kHz,SNR and SFDR are 83.32dB and 90.19dBc,respectively;when sampling frequency is 1MHz and input signal frequency is 100.6kHz,SNR and SFDR are 82.42dB and 90.19dBc,respectively.