Research And FPGA Implementation Of Software Radio Digital Down Conversion Technology

As the connection between analog-to-digital converters (ADC) and back-end digital signal processors (DSP) in the software defined radio (SDR) receivers, the digital down converter (DDC) is considered as one of the most key components. It is used to convert high-speed signals centered at intermediate frequency to low-speed baseband ones by frequency down process and down sampling, followed by DSPs to further process the converted signals, such as demodulation and decoding. Thus the DDC performance exerts direct influence on the stability of the whole SDR receiver system.Firstly, the research background of this topic is analyzed in this thesis, with description of ideal and practical implementation structure to explain the important role that the DDC plays. Then the current research and development of SDR platforms are introduced to show the significance of this research theme, followed by the description of the three popular methods of implementation of the DDC and the effecting factors on its performance.This thesis focuses on FPGA implementation of the DDC. Based on the concept of modularized design, the designed DDC system can be divided into three main blocks:the circuit of clock and reset management, mixer and multistage decimator. In the design of mixer, in order to obtain high-speed processing, the internal real-time numerically controlled oscillator (NCO) is implemented by using the high-speed all pipelined coordinated rotation digital computer (CORDIC), which is based on high-performance computing of Matlab and applicability and parameterized hardware design. As to the half-band filter (HBF), aimed at obtaining high-speed filter, all bit parallel pipelined distributed algorithm (DA) is proposed, in terms of the drawbacks of the existing DAs. Then for the cascaded integrator comb (CIC) filter design, cutting word width of output in each stage for further reduces of FPGA resources occupancy is done with Hogenaur theory.In order to verify the design, programming with Matlab to test the feasibility of system design and algorithms comes first, followed by using Verilog hardware description language (HDL) to implement the DDC circuit on FPGA with Xilinx ISE 12.3 platform. Simulation is done with Modelsim 6.5 as to each key modular function block with results showed. After the overall function simulation of system, the DDC is downloaded onto the FPGA for hardware test. Finally, design’s validity is proved by verification on hardware board by inputting a signal centered at 30 MHz sampled with 200 MHz clock frequency. It can be seen from the experimental results that the designed digital down converter satifies the project requirements with a down sampling factor of 64 and low-speed baseband signal of a 3.125MHz sampling rate outputted.