FPGA-based High Performance Network Function Accelerating Platform

Network function virtualization(NFV)decouples network functions(NFs)from expensive dedicated network devices and run software network functions in commodity servers,making them deployed and operated flexibly.However,when it comes to deep packet processing of NFs,one has to use many CPU cores to handle complex packet processing at line rate.On the other hand,owing to its high concurrency and programmability,FPGA has the feasibility and potential to accelerate deep packet processing.However,the programmable logic blocks on an FPGA board are very limited and expensive.Deploying the entire NF on FPGA is thus resource-demanding.Further,FPGA needs to be reprogrammed when the NF logic changes which can take hours to synthesize the code to generate new programs,hindering the rapid deployment of NFs.To solve the above-mentioned key challenges of FPGA in software NF performance acceleration,a Dynamic Hardware Library(DHL)-based FPGA-CPU co-design framework can ensure both high performance and flexibility for software NF platform:(1)It implements accelerator modules to perform deep packet processing in FPGA,abstracts these accelerator modules as a hardware function library,and provides a set of DHL programming APIs for developers.Enabling the complex processing of NFs to be offloaded to FPGA,while the simple processing still resides in CPU.Thus it supports implementing and deploying multiple NFs in the FPGA-CPU architecture flexibly,fast and cost-effectively with the advantages of universality and ease of programming;(2)The framework adopts and organically combines a series of practical optimization techniques,such as lock-free communication queues,user-mode I/O,NUMA-aware memory allocation,batch processing,and polling,to maximize the overall network performance.(3)Experimental results demonstrate that DHL framework greatly reduces the programming efforts for software developers to access FPGA,brings significantly higher throughput and lower latency over CPU-only implementation,and maximize the resource utilization of FPGA over FPGA-only implementation.