Hardware Design And Implementation Of Secure Hash Algorithms SM3/SHA256/SHA3

Hash algorithm is a kind of one-way hash function.It is a cryptographic algorithm that maps arbitary-sized message to a fixed-sized digest.It is widely used in message authentication,the generation of individual password file,virus detection,financial services and secturity protocols.With the rapid development of information technologies,the era of big data has coming.Therefore the need for high-performance hardware design of hash algorithms has become increasingly strong.As a proprietary cryptographic hash algorithm developed by China,SM3 has many applications in the commercial field.SHA-256 is gradually replacing the cracked MD5 and SHA-1,and has broad application prospects.In addition,NIST has also released the latest hash algorithm standard SHA-3.Based on the above background,this paper focuses on the high throughput hardware implementations of SM3,SHA-256,and SHA-3 series hash algorithms.Different improvement schemes are used for different algorithms.The implemented hardware designs in this paper are as follows:(1)For the hash algorithm SM3,high throughput design based on ASIC and FPGA is completed.Through the multi-in-one structure,optimizing the adder,removing multiple selectors and XOR gates in the critical path,the goal of improving throughput is achieved.Using the device Stratix III to complete the FPGA performance verification,the throughput can achieves 2.56 Gbps.The ASIC designs are simulated by modelsim and synthesized by DC tools.Based on the SMIC 65 nm technology,the throughput of the eight-in-one architecture can reach 7.47 Gbps.(2)In the SHA-256 algorithm implementation,using a simpler compression function and combining pre-computation,the SHA-256 algorithm is optimized for clock frequency and throughput.On the Stratix III series EP3SE80F1152C2 device,the clock frequency of signal round structure can achieves 222.32 MHz.The multi-in-one schemes complete accomplishes the high throughput design.By pre-computation idea,the adder,the AND gate and the OR gate in the critical path of the mult i-in-one structure are removed.The throughput of the eight-in-one architecture can reachs 10.59 Gbps by the SMIC 65 nm technology.By deep-pipeline,high-throughput design of SHA-256 algorithm for multiple text files is implemented.At the same time,the number of registers in message word extension module is optimized inorder to reduce the area occupation.By SMIC 65 nm technology,for multiple text files,the throughput of deep-pipeline architecture can reach 492.3Gbps.(3)Four hash algorithm standards SHA3-224,SHA3-256,SHA3-384,and SHA3-512 of SHA-3 series are implemented in one hardware design,which increases flexibility of hardware circuit.Pipeline design is used to design data padding and iterative compression modules.Besides the area is optimized and the delay of the critical path is reduced.Based on SMIC 65 nm technology,the hardware architectures supporting SHA3-224,SHA3-256,SHA3-384,and SHA3-512 can achieve 37 Gbps.