A High-Throughput Implementation Of Partially Unrolled SHA-1 And SHA-2

The SHA hash function were selected for Digital Signature Algorithm (DSA) [1], as specified in the Digital Signature Standard (DSS), and whenever a secure hash algorithm is required for federal applications. The latter hash functions are used widely in the field of communications, where until nowadays throughput of the cryptographic system was not required to be high. However, since the use of the HMAC in the IPSec [2], e-payment and VPN applications, the throughput of the cryptography system, especially the server, has to reach the highest degree of throughput. In these applications that transmission and reception rates are high, any latency or delay on calculating the digital signature of the data packet leads to degradation of the network's quality of service. Software implementations are presenting unacceptable performance for high-speed applications. Additionally, most of the proposed introduced to the market tend to be as small as possible.Hash functions play an important role in modern cryptography. A new high-throughput implementation of SHA which is based on FPGA is proposed, combining two popular hardware optimization techniques, namely"partially unrolling"and"path optimization". The result can be easily adopted by embedded system, providing a high degree of security. Compared to other competitive designs, the proposed implementation offers a higher encrypting speed (almost 1.7 times increase), while keeping small-size and similar frequency.