Research On Signal Integrity Analysis And Optimization Design Of High Speed Serial Link Based On PCIe Gen4 Protocol

Facing the arrival of 5G era,the requirement of equipment for processing data volume and data integrity is increasing gradually.High-speed serial link system is affected by many factors,such as power,bandwidth,interconnection density and signal integrity.With the development of serial link system towards high density,high speed,low voltage,low power consumption and high current,the data transmission rate has increased significantly.The design of high-speed serial link signal integrity has brought great challenges to engineers at home and abroadThis dissertation gives a brief summary of signal integrity analysis.Based on the Maxwell equations,the transmission line theory and scattering parameters are introduced.the transmitter,channel,receiver,timing jitter and system margin allocation are studied.Then the influence of the via hole part on signal integrity is studied in detail.Combined with the through via hole circuit model,3D magnetic field modeling and time domain simulation,the size of the via hole residual pile,the size of the via hole and the via hole arrangement are worked out.Hole process design rules are independently modeled,simulated and validated.to summary the best design scheme.Then according to this rule,design a server motherboard product,and the signal integrity of the link system is simulated and verified by experiments.Firstly,the circuit model of via hole is analyzed.Through circuit model and equivalent circuit,the influence factors of via hole on signal integrity are analyzed theoretically,and the correlative points between the factors and corresponding via hole parameters are also discussed.Secondly,through three-dimensional magnetic field modeling and time-domain simulation,the relationship between signal reflection,attenuation,crosstalk and residual pile,size and arrangement in the design of via hole is analyzed concretely,and the optimal design rules of parameters for ensuring signal integrity are studied.Then,a link system supporting 16Gbps PCIe Gen4 protocol is built by using the design rules.Finally,the passive and active transmission channel simulation requirements of PCIe Gen4 are passed.Finally,in order to verify the accuracy and industrial practicability of the design scheme of via-passing process parameters and signal simulation,a server motherboard is designed and manufactured,and a complete test platform of link system is established.Electrical test and data pressure test are carried out according to the actual standard of industrial application.Based on the design rules,the server motherboard link system can meet the requirements of electrical performance,data pressure and bit error rate of PCIe Gen4 protocol by testing the whole link system.Therefore,the new design rules are studied in this paper,which have good engineering accuracy and industrial practical value,and can be popularized and applied in the design of similar high-speed serial links.