High-Speed Circuit Design And The Application For Board Circuit

In recent years,advances in photolithography and IC manufacturing technology, which drive Moore's Law, means the features sizes on-chip will always decrease. This has an important impact. As the gate channel length decrease, the switching time of each gate will decrease. Shorter switching time means shorter rise time for the output drivers and higher clock frequencies possible. Nearly all signal integrity and power integrity problems get worse with shorter rise time. In the worst situation, these problems may lead to system collapse.When we entered the 21st century, we entered a new era for electronic products. Shrinking design cycle times means the product must work the first time. We do not have the luxury of multiple build-it, test-it, re-design-it loops. If signal integrity and power integrity effects are not taken into account right at the beginning and designed out, products will fail. Many kinds of high-speed circuit design theories come into being in this background.The theory of transmission line with no resistive losses is the base of high-speed circuit design in board-level. Signal characteristics must be analyzed in high-speed PCBs. And the reasons to effect signal integrity problems, the methods to solve them are also researched at the very start. Crosstalk exists in digital circuits extensively. That how digital times and signal integrity are influenced by crosstalk and the methods to reduce the crosstalk is discussed in the nest charter. In reality, there are DC losses, dielectric losses, and skin effect in nonideal transmission lines. These nonideal factors are analyzed in charter 4. Power integrity is another important problem in high-speed circuit design area. The effects such as system integrity, simultaneous switching noise and nonideal current return path that can devastate a digital design are researched in the last charter.