The Design And Implementation Of Satellite Antenna Amplitude-phase Measurement System

As an important part of the satellite, antenna and its related research projects are concerned,especially the huge market demand of antenna measurements equipment and products.So the amplitude and phase measurement detection system has important significance and great value for development.This thesis researched an amplitude and phase detection system,which services for satellite antenna near- field level system measurement system and responsible for completing the RF signal receiving and amplitude-phase calculations.This paper analyzed the context of satellite antenna measuring amplitude-phase detection technology and the current situation in domestic and international research,studied the framework of satellite antenna measurement system,built the structure and components of amplitude and phase detection systems,deduced an amplitude and phase detection method of multiple spread spectrum signal.Then based on the specific targets of the actual project,the author designed the amplitude-phase detection system,divided it into various functional modules,and discussed the des ign ideas of each module respectively.Finally,studied the design and implementation of the FPGA-based filter in signal processing portion.At the part of filter design and achieve,the author studied and discussed the design methods and implementation procedure of a new kind of filter.This section discussed the multiplexing and decimation concepts and their application principles in the filter,presented a design idea that conjunct both multiplexing and decimation in the traditional FIR filter.Then according to the filter performance and MATLAB obtained design parameters.Using Vivado as the development tool, researched the design methods of multiplexed decimation filter from the address control and timing control two aspects in detail,through software simulation shows the theoretical feasibility of combining multiplexing with decimation in a filter,and discussed the implementation process of the timing and address on the FPGA detailedly.Finally got the actual filter’s filtering results on the FPGA chip by mining number through software virtual port,which compared with filtering results of theory filter generated by MATLAB.The result for sets of data is actual value and the theoretical value from several tests are consistent,which examined the reliability and fea sibility of the filter.This filter reduced the data rate 4 times, at the same time, reduced the number of multipliers from 64 to 6, and decreases the number of adders to the original 1/6, greatly reduces the use of FPGA resources.