Research On Channel Coding And Decoding Technology In Millimeter Wave High Speed Communication

As the 5G puts forward higher requirements for high-speed,low-latency,high-reliability and other services,millimeter wave communication links have become an important transmission technology in modern communications.Aiming at the anti-interference problem in millimeter wave communication,this article will use channel coding and decoding technology to analyze and solve,which is to ensure the high reliable transmission of data in the communication system.In order to meet the application requirements of low latency and high rate in millimeter wave communication systems,this article mainly studies convolutional codes and Low Density Parity Check(LDPC)codes.For low latency and high rate applications scenarios,convolutional codes can be adopted.For large data volumes applications scenarios,LDPC codes can be adopted.This article first describes the basic principles of channel coding and decoding in millimeter wave communications,focusing on discussing convolutional codes and Quasi-Cyclic LDPC(QC-LDPC)codes.Then analyzes the various algorithms of channel coding and decoding,which including Viterbi decoding algorithm and LDPC decoding algorithm,in which Trellis is adopted to derive the Viterbi decoding process in detail.Then use Matlab R2020 a software platform to build the channel encoding and decoding system,and make emulational comparisons of the four decoding algorithms of LDPC codes,and choose using Normalized Mini-Sum(NMS)algorithm and determine its parameters.Finally,the hardware design of convolutional code and LDPC code codec is implemented on FPGA.For the low-delay design of Viterbi decoder,this article chooses the(2,1,7)convolutional code of 1/2 code rate to make the hardware implementation.Its data output delay is 79 clock cycles.After the synthesis that using the Artix7 platform that based on Xilinx company,its maximum operating frequency can reach 203 MHz,and the 10 parallel channels,the data transmission rate can reach 1256 Mbps.The results show that the decoder supports gigabit-level transmission rate and meets the target requirements of low delay and high rate.For the design of a hierarchical and partially parallel LDPC code decoder,after FPGA chip synthesis,its maximum operating frequency can reach 232 MHz.And when the number of iterations is 8,its throughput can reach 811.53 Mbps,which meets the expectation of high throughput aims.