The Technology Research Of Channel Encoding And Decoding For The Ultrashort Wave Digital Radio With High-speed

With the advent of the information age of the21st century, the development of computer andcommunication technology change quickly, digital information storage and exchange are increasingeveryday, and human requirements for the accuracy and reliability of information transmission arealso increasing. Channel codec technology can detect and correct random errors and burst errorsduring the information transmitting, so it can improve the communication quality. With the study ofchannel encoding and decoding technology, ensuring that information on noisy VHF channel cantransmit with the highest accuracy, lowest complexity, closer to the Shannon transmission rate, andthe most efficient and reliable to meet the requirements of high-speed digital ultrashort wave radio,which meet the needs of the future battlefield.LDPC code is a channel coding scheme based on a map and iterative decoding, whichperformance is very close to the Shannon limit and has a strong anti-jamming correction capabilitywith low complexity. So it becomes a strong competitor in modern communication system inchannel encoding. For the past few years, with the theory of LDPC codes continues becoming moreand more mature, the hardware implementation will become a reality, and it has began to be used innext-generation wireless communication systems. This paper focuses on the performance of LDPC(Low Density Parity Check) code mainly, and a comprehensive comparative analysis with RS(Reed-Solomon) codes is made. In this paper, main work and innovation points are as follows:(1) A brief review of development history about channel codec technology background is made.Then the RS code and LDPC code in the current situation of the implementation and applicationfield are analyzed. In order to design a kind of better performance and lower complexity of LDPCcode decoder, a comprehensively understanding for the construction method of code in the channelcoding and decoding algorithm must be learned and understood at first.(2) In order to further reduce the complexity of the LDPC’s decoding algorithm, based on theclassical BP decoding algorithm, making an in-depth study of iterative decoding algorithm inprobabilistic domain and logarithmic domain derived from this algorithm. According to thecharacteristics of the LDPC codes and the disadvantages of the LDPC’s decoding, this paperintroduced a practical stronger APP LLR which improved decoding algorithm of LDPC iterationalgorithm.The algorithm can make multiplication into additive operation,which can greatly reducethe complexity of the decoding algorithm.(3) In order to construct simple, efficient, and easy to implement practical "good" code, RScode and LDPC code simulation system are built based on MATLAB simulation platform. Firstly, for the AWGN channel model of different code length, bit rate and the number of iterations of theRS code and LDPC code performance are simulated; Further, LDPC code and RS code in rural,urban, coastal and suburban four scene performance are also simulated by selecting the VHF bandof small-scale multipath fading channel model; finally, the performance of RS codes and LDPCcodes algorithms are analyzed and compared in the channel model of AWGN and VHF bandsaccording to the simulation figure. The simulation results show that LDPC code has more excellentperformance of error correction than the RS code during the long and medium code, especiallywhich is more prominent performance at high bit rate.(4) Through the performance simulation of sum product algorithm (SPA) in the probabilitydomain and iterative APP LLR algorithm in the log domain, we can see iterative APP LLRalgorithm can reduce complexity with less performance loss. Further, choosing the iterative APPLLR algorithm, combine with VHF band channel model under different terrain conditions, obtainedthe performance simulation of LDPC’s encode and decode system. Theoretical analysis andsimulation results show that the LDPC code based on iterative APP LLR algorithm can have a goodprospect of engineering application with simple realization and excellent performance.(5) This paper gives the FPGA hardware design scheme of LDPC code’s encoder and decoder.Based on ISE11.4, modelsim6.5software platform and Verilog HDL language programming torealize the design of the QC-LDPC encoder through the shift register adder accumulator (SRAA).In order to realize the decoder easily, based on sum-product decoding algorithm of LDPC codes, thedecoder structure scheme of hierarchical fixed min-sum decoding algorithm is given, which has acertain guiding significance to the hardware realization of LDPC code.